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AS73211

Functional Description

Datasheet

• PUBLIC

DS000556

• v3-01 • 2018-Feb-07

│ 43

7.21

I²C General Procedure to start with the AS73211

After applying the power supply voltage the AS73211 is in the Configuration state, but in Power Down.

The User can now set up the device for the application by writing the control registers. The success of

the configuration can be proven by reading the control registers.

Before a measurement can be started the state must be changed to the Measurement state. The last

three bits (DOS) of the register OSR should be loaded with 011b. Now a conversion can be started

with the measurement mode, which is selected by CREG3:MMODE. A falling slope of the output pin

READY indicates the start. The rising edge at pin READY signalizes the end of conversion and the

measurement results can be read via I²C communication.

If a new configuration should be implemented, the device’s state has to be changed to Configuration

state. Therefore the value 010b should be written into the bits OSR:DOS. This operation resets all

measurement result registers to 00h, while the configuration registers keep their actual values. The

new configuration can be done now.

Figure 42:

Example of Addressing the AS73211 to Read the Configuration Registers Starting at Address

0h with “automatically incremented values” After Power-On Reset or Software Reset

(OSR:SW_RES)

Figure 43:

Example of Addressing the AS73211 to Read the Measurement Result Registers Starting at

Address 4h

The access of the result register bank with 2 byte each address (starting with the low byte), which is

only possible within the Measurement state, has a special feature (see

Figure 43). Reaching the last valid result register address (4h or 6h if SYND mode is activated with

CREG2:EN_TM = ‚1‘) the next result register address is the default one 2h during read on. The

setback to result register address 2h in Measurement mode does not take place if an address was set

above the valid addressable space.

06h

9Ch

CBh

SLAVE

ADDR.

R/W

1 1 1 0 1 0 0

E8h

address CREG1

write EDGES

write BREAK

10h

52h

01h

data transferred from slave to master

data transferred from master to slave

A: acknowledge

NA: not acknowledge

write CREG1

write CREG2

write CREG3

S: START cond.

Sr: repeated START condition

P: STOP cond.

SLAVE

ADDR.

R/W

1 1 1 0 1 0 0

E8h

04h

address MRES3

SLAVE

ADDR.

1 1 1 0 1 0 0

E9h

MRES1

read low byte

read high byte

R/W

MRES3

reg. addr.:

read low byte

read high byte

. . . NA P

data transferred from slave to master

data transferred from master to slave

A: acknowledge

NA: not acknowledge

P: STOP cond.

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