AS73211 datasheet(51/66 Pages) OSRAM

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AS73211

Datasheet

• PUBLIC

DS000556

• v3-01 • 2018-Feb-07

│ 50

Figure 50:

Configuration Register 3 (CREG3)

– Address 8h

CREG3

NAME

VALUE [b]

CONFIGURATION

bit 7 to 6

MMODE

CONT mode (continuous measurement)

01 (1)

CMD mode (measurement per command)

SYNS mode (externally synchronized start of

measurement)

SYND mode (start and end of measurement are externally

synchronized)

bit 5

Reserved (2)

bit 4

0 (1)

Standby is switched OFF

Standby is switched ON

bit 3

RDYOD

0 (1)

Pin READY operates as Push Pull output

Pin READY operates as Open Drain output

bit 2

Reserved (2)

bit 1 to 0

CCLK

00 (1)

Internal clock frequency fCLK = 1.024MHz

Internal clock frequency fCLK = 2.048MHz

Internal clock frequency fCLK = 4.096MHz

Internal clock frequency fCLK = 8.192MHz

(1)

Default value after power-on reset and software reset.

(2)

The default value after power-

on reset and software reset is ,0‘ as well as the recommended write value.

The bits CREG3:MMODE specify the measurement mode, which should be compatible to the given

application.

The bit CREG3:SB controls the operational state Standby of the AS73211. Within Standby state the

power consumption of the device is reduced, but the internal circuit is ready to continue after 4 µs

wake-up time by switching off Standby.

With bit CREG3:RDYOD the output pin READY can be changed from push pull to open drain

behavior. The open drain output allows running two or more AS73211 at the same time connected to

one READY line with pull-up resistor. As long as one device still measures, the READY line is low

active.

The internal clock frequency fCLK is controlled by the bits of CREG3:CCLK. Higher clock rates result in

shorter conversion times for the measurement. But take care of CREG1:GAIN

– with higher

frequencies than 1 MHz in some cases the irradiance responsivity is reduced (see Figure 35).

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