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AS73211

Datasheet

• PUBLIC

DS000556

• v3-01 • 2018-Feb-07

│ 53

Figure 54:

Status Register (STATUS)

– Address 0h

BREAK

NAME

DESCRIPTION

OUTCONVOF (1)(2)

Digital overflow of the internal 24 bit time reference OUTCONV

MRESOF(2)

Overflow of at least one of the measurement result registers MRES1 …

MRES3

ADCOF(2)

Overflow of at least one of the internal conversion channels during the

measurement (e.g. caused by pulsed light)

– analog evaluation is made

LDATA (3)

Measurement results in the buffer registers were overwritten before they

were transferred to the output result registers. A transfer takes place as

part of an I²C read process of at least one register of the output register

bank.

NDATA (4)

New measurement results were transferred from the temporary storage to

the output result registers.

NOTREADY

‚0‘: Measurement process is finished or not yet started

‚1‘: Measurement is in progress

(corresponds to the inverted signal at output pin READY)

STANDBYSTATE

,0‘: Standby state is switched OFF

,1‘: Standby state is switched ON

POWERSTATE

,0‘: Power Down state is switched OFF

,1‘: Power Down state is switched ON

(1)

Overflow of the internal 24-bit conversion time counter

– only possible in SYND mode with externally synchronized start

and stop of conversion.

(2)

The status flag is generated while a measurement is in progress. It always matches to the actual results of the output

(3)

A reading process of the register STATUS always resets this status flag.

(4)

A reading process of the register STATUS and/or at least one result register always resets this status flag.

The bit STATUS:OUTCONVOF shows an overflow of the 24 bit counter of the internal reference for

the conversion time. This can only occur in SYND mode with CREG2:EN_TM = ‚1‘ and in case of

accordingly long externally given conversion times. After a counter overflow the counter starts again

from zero.

The bit STATUS:MRESOF

shows an overflow in one or more result registers of MRES1 … MRES3.

This can only happen if the conversion time is longer than 216

(CREG1:TIME = 7…15 dec) in

accordance with a higher input signal. The overflowed register stops at its maximum value FFFFh.

With the bit STATUS:ADCOF an input signal overdriving is signalized, which could occur during the

measurement cycle limited in time, so that no overflow of the result registers (MRESOF) is necessarily

produced. But the measurement results are not correct in this case. To eliminate this problem the

irradiance responsivity Re of the sensor has to be decreased via CREG1:GAIN.

The status bits OUTCONVOF, MRESOF and ADCOF always correspond to the actual content of the

measurement result registers

MRES1…3.

The bits STATUS:LDATA and STATUS:NDATA show the status of the measurement results. At the

end of each measurement cycle, the results of the counters are stored into buffer registers. The flag

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