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AS73211

Functional Description

Datasheet

• PUBLIC

DS000556

• v3-01 • 2018-Feb-07

│ 38

Figure 36:

Relation of the Measurement Result to the Conversion Time Without Divider Respectively

Prescaler

Figure 36 shows the width of the register for the conversion time (OUTCONV), which represents the

internal resolution of the A/D conversion. Furthermore the measurement result (MRES[1…3]) is

shown, which is 16 bits wide. For all conversion times from 210 to 216 there is no need to use the

divider, because OUTCONV is limited to the conversion time length.

For conversion times bigger than 216 the conversion result is longer than 16 bits. Without the function

of the divider, the result contains always the 16 least significant bits. Now the divider makes it possible

to access most significant bits by shifting the 16-bit resolution of the measurement result over the

possible range of the resolution given by the conversion time register (OUTCONV).

Figure 37 shows an example, where CREG2:DIV = 2dec and therefore the divider factor is 23. MRES

corresponds now to the bits 18 to 3 of register OUTCONV and therefore the Least Significant Bits and

the Full Scale Range are 8 times higher than in case of the divider is not used.

Figure 37:

Relation of the Measurement Result to the Conversion Time with Enabled and Set Divider

7.15

Conversion Time Measurement in SYND Mode

In case of SYND measurement mode the conversion time is fully controlled by the external signal at

pin SYN. The relative deviation of this time to the internal clock frequency2 can produce some

deviations in the conversion result. However, this time can be measured in time units of the internal

system clock extended up to 24 bits. It gives the opportunity to recalculate the measured input light

more precisely (see chapter “Transfer Function”). Even further, the measurement result can be

compensated for any deviation, which can occur in the clock frequency due to temperature or supply

2 The system clock is internally generated and is subject to technological tolerances, which means that clock frequencies of

different devices may vary

12 11 10 9 8 7 6 5 4 3 2

19 18 17 16 15 14 13

23 22 21

12 11 10 9 8 7 6 5 4 3 2

15 14 13

OUTCONV

MRES

CREG2:EN_DIV = ‚0'

12 11 10 9 8 7 6 5 4 3 2

19 18 17 16 15 14 13

23 22 21

12 11 10 9 8 7 6 5 4 3 2

15 14 13

OUTCONV

MRES

CREG2:EN_DIV = ‚1'

CREG2:DIV = 2 dec

DIV = 7 … 2 … 0

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