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AS73211 数据表(PDF) 43 Page - OSRAM GmbH |
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AS73211 数据表(HTML) 43 Page - OSRAM GmbH |
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43 / 66 page ![]() Document Feedback AS73211 Functional Description Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 42 A shortened read sequence is also possible as shown in Figure 52. With the default of the bit OPTREG:INIT_IDX = ‚1‘ (see Figure 52) the internal address pointer starts at register address 2h if Measurement state is activated (OSR:DOS = 011b) and if Configuration state is activated (OSR:DOS = 010b) the internal address pointer starts at register address 0h. 7.20 I²C Addressable Register Space Figure 41 shows the overview of the internal registers of the AS73211, which can be accessed via I²C interface. The control register bank can only be accessed in the configuration state and the registers are all 8 bits long. The output registers can only be accessed in the measurement state. They are read-only registers and 16 bits long, except OUTCONV, which is 24 bits long. OUTCONV is separated into two parts to fit into the output register’s structure. OUTCONV_L contains the first lower bytes and OUTCONV_H contains the most significant byte of OUTCONV in the first byte. The second byte is 00h. The AS73211 transfers the output data registers with the least significant byte first. The output register data transfer can start at any address. If during the sequential data read the highest possible address is achieved (CREG2:EN_TM = ‚0‘: address 4h; CREG2:EN_TM = ‚1‘: address 6h), the internal pointer is reset to the address 2h so that the next transferred data byte corresponds to the low byte of MRES1. However, the maximum number of output data transferred must not exceed a total number of bytes accessible at all (6 bytes if conversion time measurement (CREG2:EN_TM) is not activated otherwise 10 bytes). The register OUTCONV is only available in case of bit CREG2:EN_TM is set to ‚1‘. Figure 41: Register Overview ADDRESS (1) [hex] ACCESS IN CONFIGURATION STATE ACCESS IN MEASUREMENT STATE WRITE READ WRITE (1 BYTE) READ (2 BYTES) 0 OSR OSR OSR + STATUS 1 – – TEMP 2 – – – MRES1 (X) 3 – – MRES2 (Y) 4 – – MRES3 (Z) 5 – – OUTCONV_L (2) 6 CREG1 – OUTCONV_H (2) 7 CREG2 – – 8 CREG3 – – 9 BREAK – – A EDGES – – B OPTREG – – (1) The 4 MSB bits of the register address are ignored. (2) OUTCONV is only available in SYND measurement mode with bit CREG2:EN_TM = ‚1‘. The least significant byte comes first. |
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