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AS73211

Functional Description

Datasheet

• PUBLIC

DS000556

• v3-01 • 2018-Feb-07

│ 41

Figure 40:

I²C Write and Read Sequences

7.18

I²C Write Protocol

The start byte consists of the slave address followed by the bit R/W set to ‚0‘ for the write direction.

The first byte after the start byte is always the device (see Figure 43) sends the address pointer to the

internal register, which the master wants to write and acknowledge. When the master sends the next

byte, it is stored in the internal register addressed before by the address pointer (REG ADDR.). Then

acknowledge is sent by the device and it internally increments the address pointer to the next internal

internal register.

If the master generates a stop condition, the transfer is aborted and a new write sequence must be

started from the beginning.

7.19

I²C Read Protocol

The start byte consists of the slave address followed by the bit R/W set to ‚0‘ for the write direction.

The first byte after the start byte is always the device (see Figure 40) sends the address pointer to the

internal register, which the master wants to read and acknowledge. After that, the master sends a

repeated start condition and repeats the slave address but with the bit R/W reversed. Acknowledge is

sent by the slave, which starts the data transfer to the master. The first transferred byte is the content

of the internal register, which was pointed by the address pointer. The master acknowledges each

transferred byte. The internal address pointer of the AS73211 automatically increments after each

transferred register, which allows a sequentially read out of internal registers. If a not acknowledge

occurs from the master it sends the stop condition next and the transfer is finished.

read sequence:

P: STOP cond.

S SLAVE ADDR. R/W A

REG ADDR. A

A: acknowledge

NA: not acknowledge

S: START cond.

Sr: repeated START cond.

DATA

NA P

. . .

Sr SLAVE ADDR.R/W

S: START cond.

P: STOP cond.

S SLAVE ADDR. R/W A

REG ADDR. A

DATA

A P

write sequence:

. . .

data transferred from slave to master

data transferred from master to slave

A: acknowledge

DATA

NA P

. . .

S SLAVE ADDR. R/W

short read sequence:

S: START cond.

P: STOP cond.

A: acknowledge

data transferred from slave to master

data transferred from master to slave

data transferred from slave to master

data transferred from master to slave

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