TCS3530 datasheet(71/106 Pages) OSRAM

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[v3-00] 2023-Jun-23

TCS3530 − Register O ver view

MEAS_SEQR_APERS_AND_VSYNC_WAIT Register

Figure 98:

MEAS_SEQR_APERS_AND_VSYNC_WAIT

Note(s):

1. Return to the Register Map (0xDC).

Addr: 0xDC

MEAS_SEQR_APERS_AND_VSYNC_WAIT

Bit

Field

Reset

Type

Bit Description

7:4

MEASUREMENT_

SEQUENCER_

VSYNC_WAIT_

PATTERN

0000b

R/W

Defines if a measurement sequence shall wait for a vsync

before starting the measurement. The bit pattern does

not represent a value but controls bitwise which

sequencer step shall be used. The leftmost position of

“0000” refers to sequencer step 3, the rightmost refers to

sequencer step 0.

3:0

MEASUREMENT_

SEQUENCER_

APERS_

PATTERN

0001b

R/W

Defines the sequencer steps where an ALS persistence

evaluation shall be performed on modulator data

selected by ALS_THRESHOLD_CHANNEL. The bit pattern

does not represent a value but controls bitwise which

sequencer step shall be used. The leftmost position of

“0000” refers to sequencer step 3, the rightmost refers to

sequencer step 0. By default step 0 is used on all

modulators.

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