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TCS3530 数据表(PDF) 72 Page - OSRAM GmbH |
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TCS3530 数据表(HTML) 72 Page - OSRAM GmbH |
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72 / 106 page  Datasheet, Public Page 71 [v3-00] 2023-Jun-23 Document Feedback TCS3530 − Register Overview MEAS_SEQR_AGC Register Figure 99: MEAS_SEQR_AGC Note(s): 1. Return to the Register Map (0xDD). MEAS_SEQR_SMUX_AND_SAMPLE_TIME Register Figure 100: MEAS_SEQR_SMUX_AND_SAMPLE_TIME Note(s): 1. Return to the Register Map (0xDE). Addr: 0xDD MEAS_SEQR_AGC Bit Field Reset Type Bit Description 7:4 MEASUREMENT_ SEQUENCER_AGC_ PREDICT_PATTERN 1111b R/W Defines the sequencer steps where predict AGC is enabled for the corresponding measurement. The bit pattern does not represent a value but controls bitwise which sequencer step shall be used. The leftmost position of “0000” refers to sequencer step 3, the rightmost refers to sequencer step 0. By default this feature is enabled for all sequencer steps. 3:0 MEASUREMENT_ SEQUENCER_AGC_ ASAT_PATTERN 1111b R/W Defines the sequencer steps where analog saturation AGC is enabled for the corresponding measurement. The bit pattern does not represent a value but controls bitwise which sequencer step shall be used. The leftmost position of “0000” refers to sequencer step 3, the rightmost refers to sequencer step 0. By default this feature is enabled for all sequencer steps. Addr: 0xDE MEAS_SEQR_SMUX_AND_SAMPLE_TIME Bit Field Reset Type Bit Description 7:4 MEASUREMENT_ SEQUENCER_ SAMPLE_ TIME_ PATTERN 0R/W This register contains one bit for each sequencer step (LSB = step 0, MSB = step 3) which selects the smux configuration from the two available variants for the corresponding sequencer step. 3:0 MEASUREMENT_ SEQUENCER_ SMUX_ PATTERN 0R/W This register contains one bit for each sequencer step (LSB = step 0, MSB = step 3) which selects the sample time configuration from the two available variants for the corresponding sequencer step. |
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