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TCS3530 数据表(PDF) 45 Page - OSRAM GmbH |
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TCS3530 数据表(HTML) 45 Page - OSRAM GmbH |
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45 / 106 page  Page 44 Datasheet, Public Document Feedback [v3-00] 2023-Jun-23 TCS3530 − Register O ver view CFG2 Register Figure 52: CFG2 Note(s): 1. Return to the Register Map (0xA3). CFG3 Register Figure 53: CFG3 Note(s): 1. Return to the Register Map (0xA4). Addr: 0xA3 CFG2 Bit Field Reset Type Bit Description 7:3 Reserved 0 2:0 FIFO_THR[2:0] 1 R/W FIFO Threshold LSB. Please see FIFO_THR for information. Addr: 0xA4 CFG3 Bit Field Reset Type Bit Description 7:6 Reserved 0 5:4 INT_PINMAP 0 R/W Interrupt Pin Mapping. Defines internal signal which is routed to the external INT pin. 00b: Default, INTERRUPT 01b: Reserved, do not use 10b: Reserved, do not use 11b: Reserved, do not use 3:2 Reserved 0 1:0 VSYNC_GPIO_ PINMAP 0R/W Vsync/GPIO Pin Mapping. Defines internal signal which is routed to the external VSYNC/GPIO pin. 00b: Default, VSYNC_GPIO_OUT 01b: Reserved, do not use 10b: Reserved, do not use 11b: Reserved, do not use |
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