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TCS3530 数据表(PDF) 42 Page - OSRAM GmbH |
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TCS3530 数据表(HTML) 42 Page - OSRAM GmbH |
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42 / 106 page ![]() Datasheet, Public Page 41 [v3-00] 2023-Jun-23 Document Feedback TCS3530 − Register Overview STATUS 5 Register Figure 48: STATUS5 Note(s): 1. Return to the Register Map (0x9F). Addr: 0x9F STATUS5 Bit Field Reset Type Bit Description 7:3 Reserved 0 2SINT_AUX 0 R/W Auxiliary System Interrupt Enable. Setting this bit will allow a system interrupt SINT as soon as an auxiliary interrupt occurs. 1 SINT_ MEASUREMENT_ SEQUENCER 0R/W Measurement Sequencer Interrupt Enable. Setting this bit will allow a system interrupt SINT as soon as invoked by a measurement sequencer event. 0SINT_VSYNC 0 R/W Vsync Interrupt Enable. Setting this bit will allow a system interrupt SINT as soon as soon as a vysnc interrupt occurs. |
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