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4LS 数据表(PDF) 58 Page - OSRAM GmbH |
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4LS 数据表(HTML) 58 Page - OSRAM GmbH |
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58 / 115 page ![]() Document Feedback 4LS Digital Interface Datasheet • PUBLIC DS000542 • v3-01 • 2022-Nov-17 114 │ 57 Figure 82: Write Cycle for Multiple Registers 8.2.3 Reading Operation The reading operation is performed by sending to read request register (RRQReg - 0x1C) the address of the register to be read. Notice that the read is an immediate operation and if performed between write/update requests and the next falling edge of LVAL, the data read is the one before the update operation. Thus, it is important to read after an update request and wait until the falling edge of next LVAL signal is sent, otherwise the read back can be invalid. Instead of waiting for the next falling edge of the LVAL, an update event can be triggered over the STS1 register by “immediate update” or “update request”. With respect to read back of registers from the ADC companding threshold registers and ADC end range registers, the register update is only performed once the A/D conversion is completed. Thus, if during the update event (falling edge of LVAL or immediate update request) an A/D conversion is running, the update of those registers is delayed until the end of the A/D conversion. Read back should only be performed afterwards. The output data of the read will be sent on the MISO line with 3 SCLK delay to the last bit from the address word (MSB first). It is only possible to read one register at a time, but it is possible to perform consecutive reads from the same segment and register. The raise of N_CS signal can be made right after the complete read of the last bit and SCLK should be placed on hold. Figure 83 presents an example for a read operation. Figure 83: Read Cycle Over SPI Interface 4 SCLK N_CS SCLK SCLK MOSI 0XF8 0X10 0XAA 0X11 0X06 0X01 0XF8 0X0F 4 SCLK 4 SCLK 4 SCLK 4 x TSCLK 4 x TSCLK 4 x TSCLK 4 x TSCLK D7 D6 D5 D4 D3 D2 D1 D0 A7 A6 A5 A4 A3 A2 A1 A0 3 x TSCLK N_CS SCLK SCLK MOSI MISO 8 x TSCLK READ BACK 3 x TSCLK 8 x TSCLK |
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