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4LS

Datasheet

• PUBLIC

DS000542

• v3-01 • 2022-Nov-17

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│ 64

9.1.6

Analogue Gain for Line 2 Register (Address 0x05)

Figure 96:

AGL2Reg

Address: 0x05

Default Value: 0x80

Access: Read/Write

Bit

Bit Name

Default

Bit Description

7:0

Analogue Gain Level

10000000b

It defines the analogue gain level in the

ADC which defines the voltage equivalent

to one ADC step (1 DN) applied to the

Line 2.

9.1.7

Black Level Offset Register (Address 0x06)

Figure 97:

BLOReg

Address: 0x06

Default Value: 0x80

Access: Read/Write

Bit

Bit Name

Default

Bit Description

7:0

Black Level Offset

10000000b

It defines the analogue black level offset

that corresponds to the ADC offset.

The Black Level value is dependent of the Vref value (register 0x0B bits[1:0]), varying 1.4 V around

the respective Vref voltage (approximately 36% below and 64% above the reference). For instance, if

Vref has a voltage of 1.8 V, and BLOReg is set to (0x00), therefore the Black level is 1.31 V. Similarly,

for the maximum value of BLOReg (0xFF), the Black level is 2.57 V. Each register step is equivalent to

approximately 5 mV.

9.1.8

Companding Threshold 1 Register (Address 0x07)

Figure 98:

CT1Reg

Address: 0x07

Default Value: 0x00

Access: Read/Write

Bit

Bit Name

Default

Bit Description

7:0

Companding

Threshold 1

00000000b

It defines, in companding mode, the first

ADC step.

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