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数据搜索系统，热门电子元器件搜索 |
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4LS 数据表(PDF) 73 Page - OSRAM GmbH |
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4LS 数据表(HTML) 73 Page - OSRAM GmbH |
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73 / 115 page  Document Feedback 4LS Register Description Datasheet • PUBLIC DS000542 • v3-01 • 2022-Nov-17 114 │ 72 9.1.20 Training Sequence 1 Line 2 Register (Address 0x13) Figure 118: TSQ1L2Reg Address: 0x13 Default Value: 0xFF Access: Read/Write Bit Bit Name Default Bit Description 7:0 Training sequence 1 11111111b Defines the 8 MSBs for word A training sequence sent over the LVDS driver of Line 2 for FPGA synchronization purposes. 9.1.21 Training Sequence 2 Line 2 Register (Address 0x14) Figure 119: TSQ2L2Reg Address: 0x14 Default Value: 0xFF Access: Read/Write Bit Bit Name Default Bit Description 7:0 Training sequence 2 11111111b Defines the 8 MSBs for word B training sequence sent over the LVDS driver of Line 2 for FPGA synchronization purposes. 9.1.22 Training Sequence 3 Line 2 Register (Address 0x15) Figure 120: TSQ3L2Reg Address: 0x15 Default Value: 0xAA Access: Read/Write Bit Bit Name Default Bit Description 7:0 Training sequence 3 10101010b Defines the LSBs for word A and B training sequence sent over the LVDS driver of Line 2 for FPGA synchronization purposes. |
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