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4LS

Functional Description

Datasheet

• PUBLIC

DS000542

• v3-01 • 2022-Nov-17

114

│ 44

Figure 63:

12-Bit Timing Clocks for Readout Mode 1-To-1

Parameters

Clocks

RST_CDS

ADC Time

707

Readout Data

644

Readout Time

670

SAMPLE

START_AD

TBTW_START_AD&RST_RAMP

TBTW_SAMPLE&START_AD

FCT

748

MTA => Line Rate

FCT = 748 => 80.21 kHz

DTI

Max Integration Time(1)

748

– 68 = 680 => 11.33 µs

Minimum LVALLow_Period

104

(1)

To use the sensor at the maximum line rate, this is the maximum integration time possible. When it comes to the

minimum integration time, in theory, it is possible to use a lower integration time, but it was not tested on this

configuration. From an application perspective, using a lower integration time, does not bring significant advantages,

once the line rate cannot be higher and the system would need to increase the illumination power.

The minimum LVAL time at low between two consecutive data streams is:

Equation 8:

��_�� = �� − ��

Therefore:

��_�� = 748 − 644 = 104 ��

Below are presented the highest line rate values for readout modes of 2-To-1 and 4-To-1, maintaining

the same above sensor configuration. On these specific cases, the Readout Time is higher than the

ADC Time, therefore the MTA is calculated by Equation 2. On this case, it is possible to use the

original SAMPLE value of 1 µs (60 clocks @ 60 MHz), once will not affect the MTA, because the FCT

is only increased by 30 clocks (total of 778).

Figure 64:

12-Bit Timing Clocks for Readout Mode 2-To-1

Parameters

Clocks

Readout Data

1288

Readout Time

1318

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