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4LS 数据表(PDF) 63 Page - OSRAM GmbH

部件名 4LS
功能描述  4LS15K, 4LS10K and 4LS5K Line Scan Sensors
PDF  115 Pages
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制造商  OSRAM [OSRAM GmbH]
网页  http://www.osram.com
标志 OSRAM - OSRAM GmbH

4LS 数据表(HTML) 63 Page - OSRAM GmbH

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4LS
Register Description
Datasheet
• PUBLIC
DS000542
• v3-01 • 2022-Nov-17
114
│ 62
Address: 0x02
Default Value: 0x00
Access: Read/Write
Bit
Bit Name
Default
Bit Description
3:3
Output Mode
0b
Sets the output transmission mode.
When set to '1' the transmission is
performed at 8-bit (maximum MCLK =
80 MHz).
When set to '0' the transmission is
performed at 12-bit (maximum MCLK =
60 MHz).
2:0
PLL Division
000b
These 3 bits are responsible for the PLL
clock division configuration.
Figure 93:
Frequency Range Programmed by PLL Division
Bit 2
Bit 1
Bit 0
Division
Value
Frequency Range of MCLK
[MHz] for 12-Bit Mode
Frequency Range of MCLK
[MHz] for 8-Bit Mode
0
0
0
0
37.5
– 60
75
– 80
0
0
1
2
19
– 37.5
38
– 75
0
1
0
4
9
–19
18
– 38
0
1
1
8
4.5
– 9
9
– 18
1
0
0
16
2
– 4.5
4
– 9
9.1.4
Status 3 Register (Address 0x03)
Figure 94:
STS3Reg
Address: 0x03
Default Value: 0x00
Access: Read/Write
Bit
Bit Name
Default
Bit Description
7:7
VBL Top Bottom
Connection
0b
When set to ‘1’ connects the black level
voltage between Top and Bottom
elements.
6:6
VREF Top Bottom
Connection
0b
When set to
‘1’ connects the CDS
reference voltage between Top and
Bottom elements.
5:5
RAMP L1 L2
Connection
0b
When set to ‘1’ connects Ramp Line 1 to
Ramp Line 2 from each segment
individually.



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