4LS datasheet(62/115 Pages) OSRAM

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4LS

Datasheet

• PUBLIC

DS000542

• v3-01 • 2022-Nov-17

114

│ 61

Address: 0x01

Default Value: 0x85

Access: Read/Write

Bit

Bit Name

Default

Bit Description

4:4

Sync Bit

When set to '1' the synchronization of the

serializer phase to the main clock is

performed by an external signal.

When set to '0' automatically

resynchronize at each rising edge of start

of readout.

3:2

Immediate Update

01b

The code 10b request an immediate

update on the effective registers.

After an update event the bits will be

cleared to 01b (no immediate update).

1:0

Update Request

01b

The code 10b request an update from the

shadow registers to the effective registers

on the next falling edge of the line valid

signal.

After an update event the bits will be

cleared to 01b (no update).

These bits have to be written after each

complete set of register configurations to

make the changes active.

(1)

The Region of Interest (ROI) operation is a main feature of 4LS5K. For standard operation, using full line resolution, the

bit should be set to ‘0’.

9.1.3

Status 2 Register (Address 0x02)

Figure 92:

STS2Reg

Address: 0x02

Default Value: 0x00

Access: Read/Write

Bit

Bit Name

Default

Bit Description

7:7

2-To-1 Output

When set to ’0’, default mode 1-To-1 is

used.

When set to ‘1’ reduces the number

of outputs taps from 4 to 2 per line and

per segment.

6:6

4-To-1 Output

When set to ’0’, default mode 1-To-1 is

used.

When set to ‘1’ reduces the number

of output taps from 4 to 1 per line and per

segment.

5:5

Auto Start Readout

Activates the automatic start readout

when set

at ‘1’.

4:4

Auto Start A/D

Activates the automatic start A/D

conversion when set

at ‘1’.

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