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4LS

Datasheet

• PUBLIC

DS000542

• v3-01 • 2022-Nov-17

114

│ 77

9.1.32

Status 6 Register (Address 0x1F)

Figure 132:

STS6Reg

Address: 0x1F

Default Value: 0x05

Access: Read/Write

Bit

Bit Name

Default

Bit Description

7:7

Slow Clock ON

Internal Debug Purposes

Use default value.

6:6

Ramp Buff Half

Current

When set to ‘1’ reduces the Ramp buffer

current to half.

5:4

VREF CVC Trimming

00b

Defines the VREF voltage to be used on

all CVC on the sensor.

3:3

RAMP Connection

between Segments

When set to ‘1’ ramps reconnected

segments, connecting ramp L1 with

ramp L2 and then they are connected

between each segment.

2:2

Enable Boost VREF

CVC Buffer

Enables a higher output current on

VREF CVC buffer.

1:1

Enable Pre-charge

over SRAM

Internal Debug Purposes

Use default value.

0:0

ADC Response

Stabilization

When set to '1' the ramp have more time

to stabilize before start the A/D

conversion.

Figure 133:

VREF CVC Trimming

Bit 1

Bit 0

Vref CVC Trimming [V]

1.1 V

1.2 V

1.3 V

1.4 V

9.2

The figure below shows the mapping of all registers (default values) on a 2K5 segment, being

applicable for the remaining segments.

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