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4LS

Datasheet

• PUBLIC

DS000542

• v3-01 • 2022-Nov-17

114

│ 73

9.1.23

Test Data Serializer Line 2 Register (Address 0x16)

Figure 121:

TDSL2Reg

Address: 0x16

Default Value: 0x40

Access: Read/Write

Bit

Bit Name

Default

Bit Description

7:0

Training test data

01000000b

When the sensor is in training mode,

defines the data pattern to test the

serialization / LVDS data output blocks for

Line 2.

The register value is concatenated with

0x0A (LSB), getting a 12-bit word.

For 12-bit mode, test data is the full 12-bit

word.

For 8-bit mode, the 2 MSB and 2 LSB are

discarded to a get 8-bit test data word.

9.1.24

SRAM Mode Test 1 Register (Address 0x17)

Figure 122:

SMT1Reg

Address: 0x17

Default Value: 0x00

Access: Read/Write

Bit

Bit Name

Default

Bit Description

7:0

SRAM test data

00000000b

Defines the 8 LSB data to be written on the

SRAM.

9.1.25

SRAM Mode Test 2 Register (Address 0x18)

Figure 123:

SMT2Reg

Address: 0x18

Default Value: 0x00

Access: Read/Write

Bit

Bit Name

Default

Bit Description

7:5

N/A

000b

Not used.

4:0

SRAM test data

00000b

Defines the 5 MSB data to be written on the

SRAM.

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