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4LS

Functional Description

Datasheet

• PUBLIC

DS000542

• v3-01 • 2022-Nov-17

114

│ 26

Figure 33:

Power-On Sequence

Startup Sequence detailed description:

●

Until N_RST_SPI remains the same as above.

●

Release N_RST_SPI.

●

Enable all segments (using FPGA register to control N_CS of each 2K5 segment).

●

Write all registers, having in consideration the following:

●

STS2 Register to choose output mode: 0x00 for 12-bit or 0x08 for 8-bit.

●

STS1 = 0x09

– Perform serializer phase sync with each Start_Readout.

●

Choose appropriate CLK phase for PLL clock compensation (STS5 Reg

– Bits[5:4]). The

chosen value will depend on the user system.

●

Sending remaining registers.

●

STS1 = 0x09

– Update of all registers.

●

Release N_RST_PLL.

●

Release N_RST_LOGIC.

●

Training Sequence tracking to perform the alignment.

●

Turn on the timing to start having Data (Training mode or Pixel Data).

●

After 1 ms (to guarantee that there is at least one complete LVAL signal) STS1 is set to 0x19 to

disable the internal serializer sync (i.e. External Sync with no actual pulse

– grounded).

7.3

Conversion Cycle

The A/D conversion starts by sending a pulse on the Start_AD signal. The use of a signal to start the

A/D conversion gives the possibility to perform different integration times on the different lines and

align the middle of each lines exposure time by starting and ending each lines exposure time

individually. However, the start of A/D conversion must always be sent after the falling edge of all

Sample signals, since it will be applied to the same ADC on the Sensor. The 12-bit resolution ADC

VDDA

Digital Inputs

MCLK

N_RST_PLL

μs

VDDXX (remaining powers)

N_RST_LOGIC

>10

μs

N_RST_SPI

5 MCLK

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