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MPC860DP 数据表(PDF) 37 Page - Freescale Semiconductor, Inc |
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MPC860DP 数据表(HTML) 37 Page - Freescale Semiconductor, Inc |
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37 / 80 page  MPC860 Family Hardware Specifications, Rev. 7 Freescale Semiconductor 37 Bus Signal Timing Figure 27 provides the PCMCIA output port timing for the MPC860. Figure 27. PCMCIA Output Port Timing Figure 28 provides the PCMCIA output port timing for the MPC860. Figure 28. PCMCIA Input Port Timing Table 11 shows the debug port timing for the MPC860. Table 10. PCMCIA Port Timing Num Characteristic 33 MHz 40 MHz 50 MHz 66 MHz Unit Min Max Min Max Min Max Min Max P57 CLKOUT to OPx valid — 19.00 — 19.00 — 19.00 — 19.00 ns P58 HRESET negated to OPx drive 1 1 OP2 and OP3 only 25.73 — 21.75 — 18.00 — 14.36 — ns P59 IP_Xx valid to CLKOUT rising edge 5.00 — 5.00 — 5.00 — 5.00 — ns P60 CLKOUT rising edge to IP_Xx invalid 1.00 — 1.00 — 1.00 — 1.00 — ns CLKOUT HRESET Output Signals OP2, OP3 P57 P58 CLKOUT Input Signals P59 P60 |
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