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MPC860DP 数据表(PDF) 40 Page - Freescale Semiconductor, Inc |
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MPC860DP 数据表(HTML) 40 Page - Freescale Semiconductor, Inc |
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40 / 80 page ![]() MPC860 Family Hardware Specifications, Rev. 7 40 Freescale Semiconductor Bus Signal Timing Figure 31. Reset Timing—Configuration from Data Bus Figure 32 provides the reset timing for the data bus weak drive during configuration. Figure 32. Reset Timing—Data Bus Weak Drive During Configuration Figure 33 provides the reset timing for the debug port configuration. HRESET RSTCONF D[0:31] (IN) R71 R74 R73 R75 R76 CLKOUT HRESET D[0:31] (OUT) (Weak) RSTCONF R69 R79 R77 R78 |
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