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MPC860DP 数据表(PDF) 62 Page - Freescale Semiconductor, Inc |
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MPC860DP 数据表(HTML) 62 Page - Freescale Semiconductor, Inc |
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62 / 80 page ![]() MPC860 Family Hardware Specifications, Rev. 7 62 Freescale Semiconductor CPM Electrical Characteristics Figure 64. SPI Master (CP = 0) Timing Diagram Table 24. SPI Master Timing Num Characteristic All Frequencies Unit Min Max 160 MASTER cycle time 4 1024 tcyc 161 MASTER clock (SCK) high or low time 2 512 tcyc 162 MASTER data setup time (inputs) 50 — ns 163 Master data hold time (inputs) 0 — ns 164 Master data valid (after SCK edge) — 20 ns 165 Master data hold time (outputs) 0 — ns 166 Rise time output — 15 ns 167 Fall time output — 15 ns SPIMOSI (Output) SPICLK (CI=0) (Output) SPICLK (CI=1) (Output) SPIMISO (Input) 162 Data 166 167 161 161 160 msb lsb msb msb Data lsb msb 167 166 163 166 167 165 164 |
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