MPC860DP datasheet(70/80 Pages) FREESCALE

70 / 80 page

MPC860 Family Hardware Specifications, Rev. 7

Freescale Semiconductor

FEC Electrical Characteristics

Figure 72. MII Transmit Signal Timing Diagram

13.3 MII Async Inputs Signal Timing (MII_CRS, MII_COL)

Table 31 provides information on the MII async inputs signal timing.

Figure 73 shows the MII asynchronous inputs signal timing diagram.

Figure 73. MII Async Inputs Timing Diagram

13.4 MII Serial Management Channel Timing (MII_MDIO, MII_MDC)

Table 32 provides information on the MII serial management channel signal timing. The FEC functions correctly

with a maximum MDC frequency in excess of 2.5 MHz. The exact upper bound is under investigation.

Table 31. MII Async Inputs Signal Timing

Num

Characteristic

Min

Max

Unit

MII_CRS, MII_COL minimum pulse width

1.5

—

MII_TX_CLK

period

Table 32. MII Serial Management Channel Timing

Num

Characteristic

Min

Max

Unit

M10

MII_MDC falling edge to MII_MDIO output invalid (minimum

propagation delay)

—

M11

MII_MDC falling edge to MII_MDIO output valid (max prop delay)

—

M12

MII_MDIO (input) to MII_MDC rising edge setup

—

MII_TX_CLK (Input)

MII_TXD[3:0] (Outputs)

MII_TX_EN

MII_TX_ER

MII_CRS, MII_COL

MPC860DP 数据表(PDF) 70 Page - Freescale Semiconductor, Inc

MPC860DP 数据表(HTML) 70 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

数据表下载