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MPC860DP 数据表(PDF) 56 Page - Freescale Semiconductor, Inc

部件名 MPC860DP
功能描述  Hardware Specifications
PDF  80 Pages
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制造商  FREESCALE [Freescale Semiconductor, Inc]
网页  http://www.freescale.com
标志 FREESCALE - Freescale Semiconductor, Inc

MPC860DP 数据表(HTML) 56 Page - Freescale Semiconductor, Inc

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MPC860 Family Hardware Specifications, Rev. 7
56
Freescale Semiconductor
CPM Electrical Characteristics
11.7 SCC in NMSI Mode Electrical Specifications
Table 20 provides the NMSI external clock timing.
Table 21 provides the NMSI internal clock timing.
Figure 55 through Figure 57 show the NMSI timings.
Table 20. NMSI External Clock Timing
Num
Characteristic
All Frequencies
Unit
Min
Max
100
RCLK1 and TCLK1 width high 1
1
The ratios SYNCCLK/RCLK1 and SYNCCLK/TCLK1 must be greater than or equal to 2.25/1.
1/SYNCCLK
ns
101
RCLK1 and TCLK1 width low
1/SYNCCLK + 5
ns
102
RCLK1 and TCLK1 rise/fall time
15.00
ns
103
TXD1 active delay (from TCLK1 falling edge)
0.00
50.00
ns
104
RTS1 active/inactive delay (from TCLK1 falling edge)
0.00
50.00
ns
105
CTS1 setup time to TCLK1 rising edge
5.00
ns
106
RXD1 setup time to RCLK1 rising edge
5.00
ns
107
RXD1 hold time from RCLK1 rising edge 2
2
Also applies to CD and CTS hold time when they are used as external sync signals.
5.00
ns
108
CD1 setup Time to RCLK1 rising edge
5.00
ns
Table 21. NMSI Internal Clock Timing
Num
Characteristic
All Frequencies
Unit
Min
Max
100
RCLK1 and TCLK1 frequency 1
1
The ratios SYNCCLK/RCLK1 and SYNCCLK/TCLK1 must be greater than or equal to 3/1.
0.00
SYNCCLK/3
MHz
102
RCLK1 and TCLK1 rise/fall time
ns
103
TXD1 active delay (from TCLK1 falling edge)
0.00
30.00
ns
104
RTS1 active/inactive delay (from TCLK1 falling edge)
0.00
30.00
ns
105
CTS1 setup time to TCLK1 rising edge
40.00
ns
106
RXD1 setup time to RCLK1 rising edge
40.00
ns
107
RXD1 hold time from RCLK1 rising edge 2
2
Also applies to CD and CTS hold time when they are used as external sync signals.
0.00
ns
108
CD1 setup time to RCLK1 rising edge
40.00
ns



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