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MPC860DP 数据表(PDF) 46 Page - Freescale Semiconductor, Inc |
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MPC860DP 数据表(HTML) 46 Page - Freescale Semiconductor, Inc |
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46 / 80 page ![]() MPC860 Family Hardware Specifications, Rev. 7 46 Freescale Semiconductor CPM Electrical Characteristics Figure 44. IDMA External Requests Timing Diagram Table 16. IDMA Controller Timing Num Characteristic All Frequencies Unit Min Max 40 DREQ setup time to clock high 7 — ns 41 DREQ hold time from clock high 3 — ns 42 SDACK assertion delay from clock high — 12 ns 43 SDACK negation delay from clock low — 12 ns 44 SDACK negation delay from TA low — 20 ns 45 SDACK negation delay from clock high — 15 ns 46 TA assertion to falling edge of the clock setup time (applies to external TA) 7 — ns 41 40 DREQ (Input) CLKO (Output) |
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