2000 Sep 07

6

Philips Semiconductors

Preliminary specification

Universal Timeslot Interchange

SC2000

PIN DESCRIPTION

Pin Name

Input/Output

Pin Number

Pin Description

D_0 - D_7

I/O

33, 32, 31, 30,

29, 27, 26, 24

Data bus.

These bi-directional, tri-state lines are the SC2000s interface to the CPU data bus.

A_0, A_1

I

38, 37

Address bus. These inputs select the internal register used by a read or write operation. Normally connected to CPU address lines

A0 and A1 in 8-bit CPU systems, or A1 and A2 in 16-bit CPU systems.

CS*

I

23

Chip Select. This active low input selects the chip for a read or write operation.

I*

I

17

Bus Interface Mode Select. This input selects Intel- and Motorola-type data bus interface configurations.

0 = Intel. 1 = Motorola.

RD*

or

STRB*

I

I

22

I* = 0. Read

This active low input enables the data bus drivers to drive the CPU data bus with the contents of the internal register selected by

A_0 and A_1.

I* = 1. Strobe

During a read operation a low on this input enables the data bus drivers to drive the CPU data bus with the contents of the internal

register selected by A_0 and A_1. During a write operation data is transferred from the CPU data bus to the register selected b y

A_0 and A_1 on a low to high transition of this signal.

WR*

or

R/W*

I

I

20

I* = 0. Write

During a write operation data is transferred from the CPU data bus to the register selected by A_0 and A_1 on a low to high

transition of this signal.

I* = 1. Read/Write

This input selects between a write operation (R/W* = 0) and a read operation (R/W* =1).

RESET

I

18

Reset.

This active high input forces all outputs to tri-state, and resets the SC2000 chip.

CLK_IN

I

50

Local clock input.

SYNC_IN

I

52

Local sync input.

SI

I

39

Serial input.

Local serial bus data input line.

SO

O

43

Serial output.

Local serial bus data output line.

TXD

I

54

Transmit data

SCbus Message Bus transmit data input line.

INT

O

35

Interrupt Request.

Active high interrupt request output line.

SCLKx2* or

CLKT

I/O

I

55

Register bit C_4 = 0. SCbus System clock x 2.

Register bit C_4 = 1. PEB Transmit clock.

SCLK or

FSYNCT

I/O

I

57

Register bit C_4 = 0. SCbus System clock.

Register bit C_4 = 1. PEB Frame sync.

RSRVD or

MSYNCT

I

I

58

Register bit C_4 = 0. SCbus Reserved.

Register bit C_4 = 1. PEB Transmit multi-frame sync.

FSYNC* or

SERT

I/O

I

59

Register bit C_4 = 0. SCbus Frame sync.

Register bit C_4 = 1. PEB Transmit serial data.

CLKFAIL

I/O

61

Register bit C_4 = 0.

SCbus Clock fail signal.

SD_0 or

L_CLKT

I/O

I/O

62

Register bit C_4 = 0. SCbus Serial data stream 0.

Register bit C_4 = 1. PEB Local resource transmit clock.

SD_1 or

L_FSYNCT

I/O

I/O

63

Register bit C_4 = 0. SCbus Serial data stream 1.

Register bit C_4 = 1. PEB Local resource transmit frame sync.

SD_2 or

L_MSYNCT

I/O

I/O

65

Register bit C_4 = 0. SCbus Serial data stream 2.

Register bit C_4 = 1. PEB Local resource multi-frame sync.

SD_3 or

L_TSX*

I/O

I/O

66

Register bit C_4 = 0. SCbus Serial data stream 3.

Register bit C_4 = 1. PEB Local resource transmit time slot enable.