SC2000 datasheet(12/44 Pages) PHILIPS

12 / 44 page

2000 Sep 07

Philips Semiconductors

Preliminary speciﬁcation

Universal Timeslot Interchange

SC2000

FSYNC Latch (C_25): When SCbus

Mode (C_4 = 0) or PEB Mode with

switching (C_7, C_4 = 11) are selected,

these bits indicate the status of the

FSYNC latch.

0 ¡ FSYNC clear

1 ¡ FSYNC set

When a PEB Mode without switching

is selected (C_7, C_4 = 01) this bit is

always clear.

CLKFAIL Latch Clear* (C_26): This bit

resets the CLKFAIL latch. Clearing this

bit to 0 clears the CLKFAIL latch and

disables CLKFAIL interrupts. Setting

this bit to 1 enables CLKFAIL interrupts.

This bit is cleared on RESET.

FSYNC Latch Clear* (C_27): This bit

resets the FSYNC latch. Clearing this bit

to 0 clears the FSYNC latch and disables

FSYNC interrupts. Setting this bit to 1

enables FSYNC interrupts.

This bit is cleared on RESET.

CLKFAIL Polarity (C_28): This bit

controls the level of the CLKFAIL signal

which will set the CLKFAIL latch. When

this bit is cleared to 0, the CLKFAIL

latch is set when the CLKFAIL signal is

“lo” (0). When this bit is set to 1 the

CLKFAIL latch is set when the CLKFAIL

signal is “hi” (1).

The “CLKFAIL = 0” interrupt mode is

used by the new clock master to deter-

mine that clock fall back has been exe-

cuted effectively. The “CLKFAIL = 1”

interrupt mode is used by the standby

clock board to detect clock failure.

This bit should only be changed when

the CLKFAIL interrupt is disabled

(C_26 = 0).

This bit is cleared on RESET.

INT Mask* (C_29): This bit controls the

interrupts generated by CLKFAIL and

FSYNC (INT = CLKFAIL + FSYNC).

When this bit is cleared to 0 all inter-

rupts are masked. When this bit is set

to 1, interrupts are enabled.

The status of this bit does not affect the

CLKFAIL Latch or FSYNC Latch bits

(C_24 and C_25), and these bits can still

be used to determine the status of the

two latches.

This bit is cleared on RESET.

INT Output Polarity (C_30): This bit

controls the active level of the INT inter-

rupt output. When this bit is cleared

to 0, then the INT output is active low.

When this bit is set to 1 then the INT

output is active high.

This bit is cleared on RESET.

INT Output Driver (C_31): This bit

controls the configuration of the INT

output driver. When this bit is cleared to

0, the INT output driver is configured as

open collector. When this bit is set to 1

the INT output driver is configured as

totem-pole.

Version/Revision Register (04H):The

Version/Revision Register is an 8-bit

read-only register used to identify the

version and revision status of a particu-

lar batch of SC2000s. It is recommended

that a test of this field be included in all

firmware interface code to ensure com-

patibility.

The initial release of the SC2000 will be

Version/Revision = 00H.

Destination Routing Memory

(80H - 9FH): The Destination Routing

Memory maps time slots from the local

SI bus onto the expansion bus. Each

location in the Destination Routing

Memory corresponds to a time slot

on the local SI bus. The contents of

each location specify a time slot on

the expansion bus.

The contents of all Destination Routing

Memory Locations are cleared on RE-

SET.

When writing data into the Destination

Routing Memory the Low Byte Data

holding a time slot number, and the

High Data Byte Register contains a 4-bit

binary field holding a Port (stream)

number. Together these two fields

uniquely identify a time slot on the

expansion bus which will be the destin-

ation for data from the local SI bus.

Version/Revision Register 1

BIT

Function

Rev 0

Rev 1

Rev 2

Rev 3

Ver 0

Ver 1

Ver 2

Ver 3

Note:

Bit 0 is the LSB of the Low Byte

Data Register.

Destination Routing Memory Map

IAR

Destination Map

80H

Channel 0

81H

Channel 1

82H

Channel 2

9FH

Channel 31

Note:

IAR = Internal Address register contents.

Channel N is equivalent to time slot N

on the local SI bus.

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