SC2000 datasheet(16/44 Pages) PHILIPS

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2000 Sep 07

Philips Semiconductors

Preliminary speciﬁcation

Universal Timeslot Interchange

SC2000

Figure 1.Microprocessor Interface Timing — Intel Bus Mode

Table 1. Microprocessor Interface Timing — Intel Bus Mode

Symbol

Parameter

Min

Typ

Max

Unit

CS* setup to WR*

↑

CS* hold from WR*

↑

RD* setup to CS*

RD* hold from CS*

WR* pulse width

WR* hold from CS*

A_[1:0] setup to WR*

↑

A_[1:0] hold from WR*

↑

D_[7:0] setup to WR*

↑

t10

D_[7:0] hold from WR*

↑

t11

RD* hold from CS*

t12

WR* setup to CS*

t13

WR* hold from CS*

t14

D_[7:0] valid delay from CS*

t15

D_[7:0] valid delay from RD*

t16

D_[7:0] valid delay from A_[1:0]

t17

D_[7:0] float delay from CS*

t18

D_[7:0] float delay from RD*

Note:

1. Timing measured with 100 pF load on D_[7:0].

t11

t12

t13

t10

t14

t15

t16

t17

t18

CS*

RD*

WR*

A_[1:0]

D_[7:0]

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