SC2000 datasheet(11/44 Pages) PHILIPS

11 / 44 page

2000 Sep 07

Philips Semiconductors

Preliminary speciﬁcation

Universal Timeslot Interchange

SC2000

Expansion Bus Data Sample

Position (C_16): When SCbus Mode is

selected (C_4 = 0) this bit determines

the location of the sampled point in the

bit cell. When this bit is cleared to 0,

sampling occurs at 50% of the bit width.

When this bit is set to 1, sampling occurs

at 75% of the bit width.

When PEB Mode is selected (C_4 = 1)

this bit has no effect, and data is always

sampled at the 50% point.

SCLKx2* must be present in order to

sample at the 75% point.

This bit is cleared on RESET.

Local Bus Data Sample Position

(C_17): When SCbus Mode is selected

(C_4 = 0) this bit determines the loca-

tion of the sample point in the bit cell.

When this bit is cleared to 0 sampling

occurs at 50% of the bit width. When

this bit is set to 1, sampling occurs at

75% of the bit width.

When PEB Mode is selected (C_4 = 1)

this bit has no effect, and data is always

sampled at the 50% point.

SCLKx2* must be present in order to

sample at the 75% point.

This bit is cleared on RESET.

SCbus Output Driver (C_18): When

SCbus Mode is selected (C_4 = 0), this

bit determines the SCbus output driver

type. When this bit is cleared to 0, the

output drivers are configured as tri-state

type. When this bit is set to 1 the output

drivers are configured as open collector

type.

When PEB Mode is selected (C_4 = 1)

this bit has no effect. PEB outputs are

always driven open collector.

All SCbus outputs are affected by this bit

with the exception of CLKFAIL and MC,

which are always driven open collector.

This bit is cleared on RESET.

SO Output Driver (C_19): This bit

determines the SO output driver type.

When this bit is cleared to 0 the output

drivers are configured as tri-state. When

this bit is set to 1 the output drivers are

configured as open collector.

When PEB Mode without switching

is selected (C_7, C_4 = 01) then SO is

always enabled.

This bit is cleared on RESET.

Local Bus Framing Format (C_20):

When SCbus Mode is selected

(C_4 = 0) this bit determines the local

bus framing format. When this bit is

cleared to 0 the local bus operates with

PEB conventional framing format.

When this bit is set to 1 the local bus op-

erates with ST-BUS framing format.

When PEB Mode is selected (C_4 = 1)

this bit has no effect.

With ST-BUS framing format selected,

SI_CLK is replaced by C4*, SI_FS by

F0*, and SI_MS by M0*. SO_CLK,

SO_FS and SO_MS are unaffected by

the status of this bit, and continue to

output PEB conventional framing.

SCLKx2* must be present, or SCLK

must be at least twice the local clock

(CLK_IN) frequency for ST-BUS fram-

ing format to be used.

This bit is cleared on RESET.

Message Channel TXD Select (C_21):

When SCbus Mode is selected

(C_4 = 0) this bit determines the

configuration of the TXD input. When

this bit is cleared to 0, the TXD input

is configured as a transparent buffer.

When this bit is set to 1 the TXD input

is configured as a latched buffer.

When PEB Mode is selected (C_4 = 1),

this bit has no effect. MC is not used in

PEB mode.

When a transparent buffer is selected

(C_21 = 0), the HDLC controller should

output TXD on the rising edge of

SO_CLK. When a latched buffer is

selected (C_21 = 1) the HDLC control-

ler should output TXD on the falling

edge of SO_CLK.

This bit is cleared on RESET.

SERT Mux (C_23, C_22): When PEB

Network Mode is selected, this two bit

field selects the source of data for the lo-

cal bus SO serial stream.

When SCbus Mode (C_7, C_6,

C_4 = xx0) or PEB Resource Mode

(C_7, C_6, C_4 = 001) are selected,

these bits have no effect.

Configuration Register 4 (03H)

CLKFAIL Latch (C_24): When SCbus

Mode is selected (C_4 = 0) this bit indi-

cates the status of the CLKFAIL latch.

0 ¡ CLKFAIL clear

1 ¡ CLKFAIL set

When PEB Mode is selected (C_4 = 1),

this bit is always clear.

ST-BUS Framing Format Replacements

PEB Conventional

ST-BUS

SI_CLK

C4*

SI_FS

F0*

SI_MS

M0*

PEB Data Source Stream

C_23, C_22

Data Source

L_SERT

(L_SERT* !L_TSX*)

+(SERT* L_TSX*)

Configuration Register 4

Bit

Function

C_24: CLKFAIL latch

C_25: CFSYNC latch

C_26: CLKFAIL latch Clear*

C_27: FSYNC latch Clear*

C_28: CLKFAIL polarity

C_29: INT Mask*

C_30: INT polarity

C_31: INT ouput driver

Note:

Bit 0 is the LSB of the Low Byte

Data Register.

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