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SC2000 数据表(PDF) 25 Page - NXP Semiconductors |
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SC2000 数据表(HTML) 25 Page - NXP Semiconductors |
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25 / 44 page  2000 Sep 07 25 Philips Semiconductors Preliminary specification Universal Timeslot Interchange SC2000 Table 6.Local Bus Interface Timing — PEB Resource Module Without Switching Symbol Parameter Min Typ Max Unit t1a CLKR, L_CLKT high time (1.544 Mbps) 323 ns t1b CLKR, L_CLKT high time (2.048 Mbps) 244 ns t2a CLKR, L_CLKT low time (1.544 Mbps) 323 ns t2b CLKR, L_CLKT low time (2.048 Mbps) 244 ns t3a CLKR, L_CLKT period (1.544 Mbps) 647 ns t3b CLKR, L_CLKT period (2.048 Mbps) 488 ns t4 SO_CLK ↑delay from CLKR↑ 35 ns t5 SO_CLK ↓delay from CLKR↓ 35 ns t6 SO_FS ↑delay from FSYNCR↑ 35 ns t7 SO_FS ↓delay from FSYNCR↓ 35 ns t8 SO_MS ↑delay from MSYNCR↑ 35 ns t9 SO_MS ↓delay from MSYNCR↓ 35 ns t10 SO delay from SERR 35 ns t11 SI_CLK ↑delay from L_CLKT ↑ 35 ns t12 SI_CLK ↓delay from L_CLKT ↓ 35 ns t13 L_FSYNCT setup to L_CLKT ↓ 5 ns t14 L_FSYNCT hold from L_CLKT ↓ 15 ns t15 SI_FS ↑delay from L_FSYNCT↑ 35 ns t16 SI_FS ↓delay from L_FSYNCT↓ 35 ns t17 SI_MS ↑delay from L_MSYNCT ↑ 35 ns t18 SI_MS ↓delay from L_MSYNCT ↓ 35 ns t19 L_SERT enable delay from L_CLKT ↑ 70 ns t20 L_SERT delay from SI 60 ns t21 L_SERT disable delay from L_CLKT ↑ 70 ns t22 L_TSX* ↓ delay from L_CLKT↑ 35 ns t23 L_TSX* ↑ delay from L_CLKT↑ 70 ns Notes: 1. Timing measured with 100 pF load on all Local Bus outputs, 200 pF 220/330 Ω termination on all PEB outputs. Open collector low to high transitions include 43 ns delay from hi-Z to 2.4 V. 2. L_TSX* occurs on time slot boundaries. |
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