2000 Sep 07

23

Philips Semiconductors

Preliminary specification

Universal Timeslot Interchange

SC2000

Table 5.Local Bus Interface Timing — SCbus Mode (8.192 Mbps)

Symbol

Parameter

Min

Typ

Max

Unit

t1

SCLKx2* low time

30.5

ns

t2

SCLKx2* high time

30.5

ns

t3

SCLKx2* period

61

ns

t4

SCLK low time

61

ns

t5

SCLK high time

61

ns

t6

SCLK period

122

ns

t7

FSYNC* setup to SCLK

↑

0

ns

t8

FSYNC* hold from SCLK

↑

15

ns

t9

SI_CLK

↓ delay from SCLK ↑

40

ns

t10

SI_CLK

↑ delay from SCLK ↑

40

ns

t11

SO_CLK

↑ delay from SCLK ↑

40

ns

t12

SO_CLK

↓delay from SCLK ↑

40

ns

t13

SI_FS, SI_MS

↓ delay from SCLK↑

45

ns

t14

SI_FS, SI_MS

↑ delay from SCLK↑

45

ns

t15

SO_FS, SO_MS

↑ delay from SCLK↑

45

ns

t16

SO_FS, SO_MS

↓ delay from SCLK↑

45

ns

t17

SO float to valid delay from SCLK

↑

40

ns

t18

SO valid to valid delay from SCLK

↑

40

ns

t19

SO valid to float delay from SCLK

↑

25

ns

t20

SI setup to SCLK

↑(50% sample position)

0

ns

t21

SI hold from SCLK

↑(50% sample position)

25

ns

t22

SI setup to SCLK

↑(75% sample position)

0

ns

t23

SI hold from SCLK

↑(75% sample position)

25

ns

t24

SD_[15:0] float to valid delay from SCLK

↑

35

ns

t25

SD_[15:0] valid to valid delay from SCLK

↑

35

ns

t26

SD_[15:0] valid to float delay from SCLK

↑

25

ns

t27

SD_[15:0] setup to SCLK

↓ (50% sample)

0

ns

t28

SD_[15:0] hold from SCLK

↓(50% sample)

25

ns

t29

SD_[15:0] setup to SCLKx2*

↑ (75% sample)

0

ns

t30

SD_[15:0] hold from SCLKx2*

↑ (75% sample)

25

ns

t31

TXD setup to SCLK

↑(registered MC)

0

ns

t32

TXD hold from SCLK

↑(registered MC)

25

ns

t33

MC delay from SCLK

↑ (registered MC)

85

ns

t34

MC delay from TXD (passed through MC)

80

ns

t35

RXD delay from MC

35

ns

Notes:

1. Timing measured with 100 pF load on all Local Bus outputs, 200 pF load on all SCbus outputs.

2. MC timing measured with 200 pF, 470

Ω pullup (4.7 K Ω/10). Open collector low to high transitions include 61 ns delay from hi-Z to 2.4 V.

3. SI_CLK, SI_FS and SI_MS shown in ST-BUS framing format. When in PEB conventional framing format SI_CLK, SI_FS and SI_MS have

identical timing to SO_CLK, SO_FS and SO_MS.

4. SO shown configured as tri-state driver.

5. SO_MS, SI_MS are free-running multi-frame synchronization signals that occur once every 16 frames.