2000 Sep 07

39

Philips Semiconductors

Preliminary specification

Universal Timeslot Interchange

SC2000

Figure 15. PEB Network Slave

Table 15: PEB Network Slave

Symbol

Parameter

Min

Typ

Max

Unit

t1

CLKT period

488

ns

t2

CLKT high time

244

ns

t3

CLKT low time

244

ns

t4

CLKR, L_CLKT

↑delay from CLKT ↑

60

ns

t5

CLKR, L_CLKT

↓delay from CLKT ↓

25

ns

t6

SYNC_IN low setup to CLKR

↓

0

ns

t7

SYNC_IN low hold from CLKR

↓

20

ns

t8

SYNC_IN high setup to CLKR

↓

0

ns

t9

SYNC_IN high hold from CLKR

↓

20

ns

t10

FSYNCR, L_FSYNCT

↑delay from FSYNCT↑

60

ns

t11

FSYNCR, L_FSYNCT

↓delay from FSYNCT↓

25

ns

t12

MSYNCR

↑delay from MSYNCT↑

60

ns

t13

MSYNCR

↓delay from MSYNCT↓

25

ns

t14

MSYNCR

↑delay from CLKR ↑

70

ns

t15

MSYNCR

↓delay from CLKR ↑

35

ns

t16

L_MSYNCT

↑ delay from MSYNCT ↑

60

ns

t17

L_MSYNCT

↓ delay from MSYNCT ↓

25

ns

Note:

1. Timing measured with 200 pF 220/330

Ω termination on all PEB outputs. Open collector low to high transitions include 43 ns delay from hi-Z to 2.4 V.

t1

t2

t3

t4

t5

t6

t7

t8

t9

t10

t11

t12

t14

t13

t15

t16

t17

CLKT

CLKR, L_CLKT

SYNC_IN

FSYNCT

FSYNCR, L_FSYNCT

MSYNCT

MSYNCR

L_MSYNCT