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SC2000 数据表(PDF) 34 Page - NXP Semiconductors

部件名 SC2000
功能描述  Universal Timeslot Interchange
PDF  44 Pages
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制造商  PHILIPS [NXP Semiconductors]
网页  http://www.nxp.com
标志 PHILIPS - NXP Semiconductors

SC2000 数据表(HTML) 34 Page - NXP Semiconductors

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2000 Sep 07
34
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC2000
Figure 12. CLK_IN, SYNC_IN — SCbus Mode (CLK_IN Divider = 1)
Table 12. CLK_IN, SYNC_IN — SCbus Mode (CLK_IN Divider = 1)
Symbol
Parameter
Min
Typ
Max
Unit
t1
CLK_IN period
488
ns
t2
CLK_IN high time
244
ns
t3
CLK_IN low time
244
ns
t4
SYNC_IN low setup to CLK_IN
↓ (PEB conventional)
10
ns
t5
SYNC_IN low hold from CLK_IN
↓ (PEB conventional)
10
ns
t6
SYNC_IN high setup to CLK_IN
↓(PEB conventional)
10
ns
t7
SYNC_IN high hold from CLK_IN
↓ (PEB conventional)
10
ns
t8
SYNC_IN setup to CLK_IN
↓ (ST-BUS)
10
ns
t9
SYNC_IN hold from CLK_IN
↓ (ST-BUS)
10
ns
t10a
SCLK
↑ delay from CLK_IN ↑ (PEB conventional)
25
ns
t10b
SCLK
↑ delay from CLK_IN ↓ (ST-BUS)
25
ns
t11a
SCLK
↓ delay from CLK_IN ↓ (PEB conventional)
25
ns
t11b
SCLK
↓ delay from CLK_IN ↑ (ST-BUS)
25
ns
t12
FSYNC*
↓ delay from SCLK ↓
30
ns
t13
FSYNC*
↑ delay from SCLK ↓
30
ns
Note:
1. Timing measured with 200 pF load on all SCbus outputs.
t1
t2
t3
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10a
t10b
t11a
t11b
t12
t13
CLK_IN (Conventional)
SYNC_IN (Conventional)
CLK_IN (ST-BUS)
SYNC_IN (ST-BUS)
SCLKX2*
SCLK
FSYNC*



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