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SC2000 数据表(PDF) 27 Page - NXP Semiconductors |
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SC2000 数据表(HTML) 27 Page - NXP Semiconductors |
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27 / 44 page  2000 Sep 07 27 Philips Semiconductors Preliminary specification Universal Timeslot Interchange SC2000 Table 7. Local Bus Interface Timing — PEB Network Module Without Swithing Symbol Parameter Min Typ Max Unit t1a L_CLKT, CLKR high time (1.544 Mbps) 323 ns t1b L_CLKT, CLKR high time (2.048 Mbps) 244 ns t2a L_CLKT, CLKR low time (1.544 Mbps) 323 ns t2b L_CLKT, CLKR low time (2.048 Mbps) 244 ns t3a L_CLKT, CLKR period (1.544 Mbps) 647 ns t3b L_CLKT, CLKR period (2.048 Mbps) 488 ns t4 SO_CLK ↑ delay from L_CLKT ↑ 35 ns t5 SO_CLK ↓ delay from L_CLKT ↓ 35 ns t6 SO_FS ↑ delay from L_FSYNCT↑ 35 ns t7 SO_FS ↓ delay from L_FSYNCT↓ 35 ns t8 SO_MS ↑ delay from L_MSYNCT↑ 35 ns t9 SO_MS ↓ delay from L_MSYNCT↓ 35 ns t10 SO delay from SERT, L_SERT 35 ns t11 SO delay from L_TSX* 35 ns t12 SI_CLK ↑ delay from LCLKR↑ 35 ns t13 SI_CLK ↓ delay from L_CLKR↓ 35 ns t14 FSYNCR setup to CLKR ↓ 5 ns t15 FSYNCR hold from CLKR ↓ 15 ns t16 SI_FS ↑ delay from FSYNCR ↑ 35 ns t17 SI_FS ↓ delay from FSYNCR ↓ 35 ns t18 SI_MS ↑ delay from MSYNCR↑ 35 ns t19 SI_MS ↓ delay from MSYNCR ↓ 35 ns t20 SERR enable delay from CLKR ↑ 70 ns t21 SERR delay from SI 60 ns t22 SERR disable delay from CLKR ↑ 70 ns Note: 1. Timing measured with 100 pF load on all Local Bus outputs, 200 pF 220/330 Ω termination on all PEB outputs. Open collector low to high transitions include 43 ns delay from hi-Z to 2.4 V. |
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