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M58PR512LE 数据表(PDF) 113 Page - STMicroelectronics |
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M58PR512LE 数据表(HTML) 113 Page - STMicroelectronics |
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113 / 119 page  M58PR256LE, M58PR512LE, M58PR001LE Command interface state tables 113/119 Table 54. Command interface states - modify table, next state 2 Current chip state command input to chip and resulting chip next state Clear SR Read ID Lock, CR, ECR Setup Lock EFA Setup Blank Check Setup OTP Setup Block Lock Confirm Lock- down Confirm Write CR/ECR Confirm Illegal Cmd or BEFP Data WSM Operation Complete 50h 90h 98h 60h 64h BCh C0h 01h 2Fh 03h 04h others ready ready lock/CR/E CR setup lock EFA block setup blank check setup OTP setup ready ready N/A Lock/CR/ECR Setup ready (sequence error) ready (lock) ready (lock down) ready (set CR) ready (sequence error) Lock EFA Block Setup ready (EFA lock) ready (sequence error) OTP setup OTP busy busy OTP busy IS in OTP busy OTP busy IS ready IS in OTP busy OTP busy WP or EFA Block WP setup WP busy WP busy N/A busy WP busy IS in program busy IS WP busy ready IS in program busy WP busy IS ready suspend WP suspend (error bits cleared) WP suspend IS in PS WP suspend N/A IS in PS WP suspend BP setup BP load 1 (give word count load (N-1)) N/A BP load 1 if N=0 go to BP confirm else go to BP load 2 (data load) BP load 2 BP confirm when count =0 else BP load 2 BP confirm when count = 0 else BP load 2 BP confirm ready (sequence error) BP busy BP busy IS in BP busy IS BP busy ready IS in BP busy BP busy IS ready BP suspend BP suspend (error bits cleared) BP suspend IS in BP suspend BP suspend N/A IS in BP suspend BP suspend Erase or EFA Block Erase setup ready (sequence error) N/A busy erase busy IS in erase busy IS erase busy ready IS in erase busy erase busy IS non- ready suspend ES (error bits cleared) ES Lock/CR/E CR setup in ES lock EFA block setup in ES IS ES N/A IS in ES ES |
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