P

S

P

SCL

SDA

VIH

VIL

VIH

VIL

A

Bit7(MSB)

Bit6

Bit0(LSB)

tw(SCLL)

tw(SCLH)

tr

tf

tsu(START)

th(START)

tsu(SDA)

th(SDA)

t(BUS)

tr

tf

tsu(STOP)

16

CDCE925, CDCEL925

SCAS847I – JULY 2007 – REVISED OCTOBER 2016

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Product Folder Links: CDCE925 CDCEL925

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Copyright © 2007–2016, Texas Instruments Incorporated

(1)

Address bits A0 and A1 are programmable through the SDA/SCL bus (byte 01, bit [1:0]. This allows addressing up to four devices

connected to the same SDA/SCL bus. The least-significant bit of the address byte designates a write or read operation.

Figure 8. Timing Diagram for SDA/SCL Serial Control Interface

9.3.4 Data Protocol

The device supports Byte Write and Byte Read and Block Write and Block Read operations.

For Byte Write/Read operations, the system controller can individually access addressed bytes.

For Block Write/Read operations, the bytes are accessed in sequential order from lowest to highest byte (with

most-significant bit first) with the ability to stop after any complete byte has been transferred. The numbers of

bytes read out are defined by byte count in the generic configuration register. At the Block Read instruction, all

bytes defined in the byte count must be read out to finish the read cycle correctly.

Once a byte has been sent, it is written into the internal register and is effective immediately. This applies to

each transferred byte regardless of whether this is a Byte Write or a Block Write sequence.

If the EEPROM write cycle is initiated, the internal SDA registers are written into the EEPROM. During this write

cycle, data is not accepted at the SDA/SCL bus until the write cycle is completed. However, data can be read out

during the programming sequence (Byte Read or Block Read). The programming status can be monitored by

EEPIP, byte 01h–bit 6.

The offset of the indexed byte is encoded in the command code, as described in Table 5.

Table 5. Slave Receiver Address (7 Bits)

DEVICE

A6

A5

A4

A3

A2

A1(1)

A0(1)

R/W

CDCEx913

1

1

0

0

1

0

1

1/0

CDCEx925

1

1

0

0

1

0

0

1/0

CDCEx925

1

1

0

1

1

0

1

1/0

CDCEx949

1

1

0

1

1

0

0

1/0

9.4 Device Functional Modes

9.4.1 SDA/SCL Hardware Interface

Figure 9 shows how the CDCEx925 clock synthesizer is connected to the SDA/SCL serial interface bus. Multiple

devices can be connected to the bus, but the speed may need to be reduced (400 kHz is the maximum) if many

devices are connected.

Note that the pullup resistors (RP) depend on the supply voltage, bus capacitance, and number of connected

devices. The recommended pullup value is 4.7 kΩ. It must meet the minimum sink current of 3 mA at VOLmax =

0.4 V for the output stages (for more details, see SMBus or I2C Bus specification).