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CDCE925, CDCEL925

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SCAS847I – JULY 2007 – REVISED OCTOBER 2016

Product Folder Links: CDCE925 CDCEL925

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Changes from Revision E (October 2009) to Revision F

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Added PLL settings limits: 16

≤ q ≤ 63, 0 ≤ p ≤ 7, 0 ≤ r ≤ 511, 0 < N < 4096 to PLL1 and PLL2 Configure Register

tables .................................................................................................................................................................................... 21

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Added PLL settings limits: 16

≤ q ≤ 63, 0 ≤ p ≤ 7, 0 ≤ r ≤ 511, 0 < N < 511 to PLL Multiplier/Divder Definition Section .... 25

Changes from Revision D (September 2009) to Revision E

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Deleted sentence - A different default setting can be programmed on customer request. Contact Texas Instruments

sales or marketing representative for more information. ...................................................................................................... 15

Changes from Revision C (December 2007) to Revision D

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Added Note 3: SDA and SCL can go up to 3.6 V as stated in the Recommended Operating Conditions table ................... 5

Changes from Revision B (August 2007) to Revision C

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Changed all values except in add rows: Original - 108, 102, 100, 96, 34.............................................................................. 6

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Changed Generic Configuration Register table RID From: 0h To: Xb ................................................................................. 19

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Added note to the PWDN description in Generic Configuration Register table ................................................................... 19

Changes from Revision A (August 2007) to Revision B

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Changed IDDPD Power-down current Typ value from 20 to 30................................................................................................ 6

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Changed II LVCMOS Input current Typ value from ±5 to ±5 Max.......................................................................................... 6

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Changed IIH LVCMOS Input current for S0/S1/S2 value from 5 Typ to 5 Max ...................................................................... 6

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Changed IIL LVCMOS Input current for S0/S1/S2 value from –4 Typ to –4 Max................................................................... 6

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Changed text of Note 4 in the DEVICE CHARACTERISTIC table......................................................................................... 8

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Changed Test Load for 50-Ω Board Environment ................................................................................................................ 11

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Changed PLL Setting table header From: OUTPUT SELECTION (Y2 ... Y9) To: OUTPUT SELECTION (Y2 ... Y5) ........ 14

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Changed Generic Configuration Register table 01h Bit 7 From: For interla use – always write To: Reserved –

always write ......................................................................................................................................................................... 19

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Changed PLL2 Configuration Register table PLL2_1N [11:4] description From: fVCO1_1 To: fVCO2_1 ................................... 23

Changes from Original (July 2007) to Revision A

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Changed the data sheet status From: Product Preview To: Production data ........................................................................ 1