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CDCE925, CDCEL925

SCAS847I – JULY 2007 – REVISED OCTOBER 2016

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Table 2. PLL Setting (Can Be Selected for Each PLL Individual)() (continued)

SSC SELECTION (CENTER/DOWN)

SSCx [3-Bits]

CENTER

DOWN

(2)

Frequency0 and Frequency1 can be any frequency within the specified fVCO range.

(3)

State0/1 selection is valid for both outputs of the corresponding PLL module and can be power down,

high-impedance state, low, or active

1

1

0

±1.5%

–1.5%

1

1

1

±2%

–2%

FREQUENCY SELECTION(2)

FSx

FUNCTION

0

Frequency0

1

Frequency1

OUTPUT SELECTION(3) (Y2 ... Y5)

YxYx

FUNCTION

0

State0

1

State1

(1)

State0 and State1 are user definable in the generic configuration

register and can be power down, high-impedance state, low, or

active.

Table 3. Y1 Setting(1)

Y1 SELECTION

Y1

FUNCTION

0

State 0

1

State 1

SDA/S1 and SCL/S2 pins of the CDCEx925 are dual-function pins. In the default configuration, they are

predefined as the SDA/SCL serial programming interface. They can be programmed to control pins (S1/S2) by

setting the relevant bits in the EEPROM. Note that the changes of the bits in the control register (bit [6] of byte

02h) have no effect until they are written into the EEPROM.

Once they are set as control pins, the serial programming interface is no longer available. However, if VDDOUT is

forced to GND, the two control pins, S1 and S2, temporally act as serial programming pins (SDA/SCL).

S0 is not a multi-use pin; it is a control pin only.

9.3.2 Default Device Setting

The internal EEPROM of CDCEx925 is preconfigured as shown in Figure 7. The input frequency is passed

through the output as a default. This allows the device to operate in default mode without the extra production

step of programming it. The default setting appears after power is supplied or after a power-down/up sequence

until it is reprogrammed by the user to a different application configuration. A new register setting is programmed

through the serial SDA/SCL interface.