6

CDCE925, CDCEL925

SCAS847I – JULY 2007 – REVISED OCTOBER 2016

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Recommended Operating Conditions (continued)

MIN

NOM

MAX

UNIT

(1)

For more information about VCXO configuration, and crystal recommendation, see VCXO Application Guideline for CDCE(L)9xx Family

(SCAA085).

(2)

Pulling range depends on crystal-type, on-chip crystal load capacitance and PCB stray capacitance; pulling range of minimum ±120 ppm

applies for crystal listed in VCXO Application Guideline for CDCE(L)9xx Family (SCAA085).

TA

Operating free-air temperature

–40

85

°C

CRYSTAL AND VCXO(1)

fXtal

Crystal input frequency (fundamental mode)

8

27

32

MHz

ESR

Effective series resistance

100

Ω

fPR

Pulling (0 V

≤ VCtrl ≤ 1.8 V)

(2)

±120

±150

ppm

VCtrl

Frequency control voltage

0

VDD

V

C0/C1

Pullability ratio

220

CL

On-chip load capacitance at Xin and Xout

0

20

pF

(1)

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.4 Thermal Information

THERMAL METRIC(1)

CDCEx925

UNIT

PW (TSSOP)

20 PINS

RθJA

Junction-to-ambient thermal resistance

Airflow 0 (LFM)

101

°C/W

Airflow 150 (LFM)

85

Airflow 200 (LFM)

84

Airflow 250 (LFM)

82

Airflow 500 (LFM)

74

RθJC(top)

Junction-to-case (top) thermal resistance

42

°C/W

RθJB

Junction-to-board thermal resistance

63.63

°C/W

ψJT

Junction-to-top characterization parameter

1.01

°C/W

ψJB

Junction-to-board characterization parameter

58.12

°C/W

RθJC(bot)

Junction-to-case (bottom) thermal resistance

58

°C/W

(1)

All typical values are at respective nominal VDD.

7.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP(1)

MAX

UNIT

IDD

Supply current (see Figure 1)

All outputs off, fCLK = 27 MHz,

fVCO = 135 MHz, fOUT = 27 MHz

All PLLS on

20

mA

Per PLL

9

IDDOUT

Supply current (see Figure 2 and

Figure 3)

No load, all outputs on,

fOUT = 27 MHz

CDCE925,

VDDOUT = 3.3 V

2

mA

CDCEL925,

VDDOUT = 1.8 V

1

IDDPD

Power-down current. Every circuit

powered down except SDA/SCL

fIN = 0 MHz, VDD = 1.9 V

30

µA

VPUC

Supply voltage VDD threshold for power-

up control circuit

0.85

1.45

V

fVCO

VCO frequency range of PLL

80

230

MHz

fOUT

LVCMOS output frequency

CDCEx925 VDDOUT = 1.8 V

230

MHz

LVCMOS

VIK

LVCMOS input voltage

VDD = 1.7 V, IS = –18 mA

–1.2

V

II

LVCMOS input current

VI = 0 V or VDD, VDD = 1.9 V

±5

µA

IIH

LVCMOS input current for S0/S1/S2

VI = VDD, VDD = 1.9 V

5

µA

IIL

LVCMOS Input current for S0/S1/S2

VI = 0 V, VDD = 1.9 V

–4

µA