Xin

Xout

Vctr

VCXO

XO

20pF

20pF

i.e.

XCSEL =10pF

20

CDCE925, CDCEL925

SCAS847I – JULY 2007 – REVISED OCTOBER 2016

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Table 9. Generic Configuration Register (continued)

OFFSET

(1)

BIT

(2)

ACRONYM

DEFAULT

(3)

DESCRIPTION

(6)

Selection of control pins is effective only if written into the EEPROM. Once written into the EEPROM, the serial programming pins are no

longer available. However, if VDDOUT is forced to GND, the two control pins, S1 and S2, temporally act as serial programming pins

(SDA/SCL), and the two slave receiver address bits are reset to A0 = 0 and A1 = 0.

(7)

These are the bits of the control terminal register. The user can predefine up to eight different control settings. These settings then can

be selected by the external control pins, S0, S1, and S2.

(8)

The internal load capacitor (C1, C2) must be used to achieve the best clock performance. External capacitors must be used only to

finely adjust CL by a few picofarads. The value of CL can be programmed with a resolution of 1 pF for a crystal load range of 0 pF to 20

pF. For CL > 20 pF, use additional external capacitors. Also, the value of the device input capacitance has to be considered which

always adds 1.5 pF (6 pF/2 pF) to the selected CL. For more information about VCXO configuration and crystal recommendation, see

VCXO Application Guideline for CDCE(L)9xx Family (SCAA085).

(9)

Note: The EEPROM WRITE bit must be sent last. This ensures that the content of all internal registers are stored in the EEPROM. The

EEWRITE cycle is initiated with the rising edge of the EEWRITE bit. A static level-high does not trigger an EEPROM WRITE cycle. The

EEWRITE bit must be reset to low after the programming is completed. The programming status can be monitored by reading out

EEPIP. If EELOCK is set to high, no EEPROM programming is possible.

(1)

Writing data beyond 30h may adversely affect device function.

(2)

All data is transferred MSB-first.

(3)

Unless a custom setting is used

(4)

The user can predefine up to eight different control settings. In normal device operation, these settings can be selected by the external

control pins, S0, S1, and S2.

02h

7

M1

1b

Clock source selection for output Y1:

0 – Input clock

1 – PLL1 clock

6

SPICON

0b

Operation mode selection for pins 14/15

(6)

0 – Serial programming interface SDA (pin 15) and SCL (pin 14)

1 – Control pins S1 (pin 15) and S2 (pin 14)

5:4

Y1_ST1

11b

Y1-State0/1 definition00 – Device power down (all PLLs in power down and all outputs in high-impedance state)

01 – Y1 disabled to high-impedance state 10 – Y1 disabled to low

11 – Y1 enabled

3:2

Y1_ST0

01b

1:0

Pdiv1 [9:8]

001h

10-bit Y1-Output-Divider Pdiv1:

0 – Divider is reset and in standby

1 to 1023 – Divider value

03h

7:0

Pdiv1 [7:0]

04h

7

Y1_7

0b

Y1_ST0/Y1_ST1 State Selection

(7)

6

Y1_6

0b

0 – State0 (predefined by Y1_ST0)

1 – State1 (predefined by Y1_ST1)

5

Y1_6

0b

4

Y1_6

0b

3

Y1_6

0b

2

Y1_6

0b

1

Y1_6

0b

0

Y1_6

0b

05h

7:3

XCSEL

0Ah

Crystal load-capacitor selection

(8)

00h – 0 pF

01h – 1 pF

02h – 2 pF

:

14h to 1Fh – 20 pF

2:0

0b

Reserved – do not write other than 0.

06h

7:1

BCOUNT

30h

7-bit byte count (defines the number of bytes which is sent from this device at the next Block Read transfer); all bytes must

be read out to correctly finish the read cycle.

0

EEWRITE

0b

Initiate EEPROM write cycle

(9)

0 – No EEPROM write cycle

1 – Start EEPROM write cycle (internal registers are saved to the EEPROM)

07h-0Fh

—

0h

Reserved – do not write other than 0

Table 10. PLL1 Configuration Register

OFFSET(1)

BIT(2)

ACRONYM

DEFAULT(3)

DESCRIPTION

10h

7:5

SSC1_7 [2:0]

000b

SSC1: PLL1 SSC selection (modulation amount). (4)

4:2

SSC1_6 [2:0]

000b

Down

000 (Off)

001 – 0.25%

010 – 0.5%

011 – 0.75%

100 – 1.0%

101 – 1.25%

110 – 1.5%

111 – 2.0%

Center

000 (Off)

001 ± 0.25%

010 ± 0.5%

011 ± 0.75%

100 ± 1.0%

101 ± 1.25%

110 ± 1.5%

111 ± 2.0%

1:0

SSC1_5 [2:1]

000b

11h

7

SSC1_5 [0]

6:4

SSC1_4 [2:0]

000b

3:1

SSC1_3 [2:0]

000b

0

SSC1_2 [2]

000b

12h

7:6

SSC1_2 [1:0]

5:3

SSC1_1 [2:0]

000b

2:0

SSC1_0 [2:0]

000b