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CDCE925, CDCEL925

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SCAS847I – JULY 2007 – REVISED OCTOBER 2016

Product Folder Links: CDCE925 CDCEL925

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Copyright © 2007–2016, Texas Instruments Incorporated

(1)

Address offset refers to the byte address in the configuration register in Table 9, Table 10, and Table 11.

The grey-highlighted bits, described in the Configuration Registers tables in the following pages, belong to the

Control Terminal Register. The user can predefine up to eight different control settings. These settings then can

be selected by the external control pins, S0, S1, and S2 (see Control Terminal Setting).

Table 8. Configuration Register, External Control Terminals

Y1

PLL1 SETTINGS

PLL2 SETTINGS

EXTERNAL CONTROL

PINS

S2

S1

S0

Y1

FS1

SSC1

Y2Y3

FS2

SSC2

Y4Y5

0

0

0

0

Y1_0

FS1_0

SSC1_0

Y2Y3_0

FS2_0

SSC2_0

Y4Y5_0

1

0

0

1

Y1_1

FS1_1

SSC1_1

Y2Y3_1

FS2_1

SSC2_1

Y4Y5_1

2

0

1

0

Y1_2

FS1_2

SSC1_2

Y2Y3_2

FS2_2

SSC2_2

Y4Y5_2

3

0

1

1

Y1_3

FS1_3

SSC1_3

Y2Y3_3

FS2_3

SSC2_3

Y4Y5_3

4

1

0

0

Y1_4

FS1_4

SSC1_4

Y2Y3_4

FS2_4

SSC2_4

Y4Y5_4

5

1

0

1

Y1_5

FS1_5

SSC1_5

Y2Y3_5

FS2_5

SSC2_5

Y4Y5_5

6

1

1

0

Y1_6

FS1_6

SSC1_6

Y2Y3_6

FS2_6

SSC2_6

Y4Y5_6

7

1

1

1

Y1_7

FS1_7

SSC1_7

Y2Y3_7

FS2_7

SSC2_7

Y4Y5_7

Address offset(1)

04h

13h

10h–12h

15h

23h

20h–22h

25h

(1)

Writing data beyond 30h may affect device function.

(2)

All data transferred with the MSB first

(3)

Unless customer-specific setting

(4)

During EEPROM programming, no data is allowed to be sent to the device through the SDA/SCL bus until the programming sequence is

completed. Data, however, can be read out during the programming sequence (Byte Read or Block Read).

(5)

If this bit is set to high in the EEPROM, the actual data in the EEPROM is permanently locked. No further programming is possible.

Data, however can still be written through the SDA/SCL bus to the internal register to change device function on the fly. But new data

can no longer be saved to the EEPROM. EELOCK is effective only if written into the EEPROM.

Table 9. Generic Configuration Register

OFFSET

(1)

BIT

(2)

ACRONYM

DEFAULT

(3)

DESCRIPTION

00h

7

E_EL

Xb

Device identification (read-only): 1 is CDCE925 (3.3 V out), 0 is CDCEL925 (1.8 V out)

6:4

RID

Xb

Revision identification number (read-only)

3:0

VID

1h

Vendor identification number (read-only)

01h

7

–

0b

Reserved – always write 0

6

EEPIP

0b

EEPROM programming Status4:

(4) (read-only)

0 – EEPROM programming is completed

1 – EEPROM is in programming mode

5

EELOCK

0b

Permanently lock EEPROM data

(5)

0 – EEPROM is not locked

1 – EEPROM is permanently locked

4

PWDN

0b

Device power down (overwrites S0/S1/S2 setting; configuration register settings are unchanged)

Note: PWDN cannot be set to 1 in the EEPROM.

0 – Device active (all PLLs and all outputs are enabled)

1 – Device power down (all PLLs in power down and all outputs in high-impedance state)

3:2

INCLK

00b

Input clock selection:

00 – Xtal

01 – VCXO

10 – LVCMOS

1 – Reserved

1:0

SLAVE_ADR

00b

Address bits A0 and A1 of the slave receiver address