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CDCE925PW 数据表(PDF) 12 Page - Texas Instruments |
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CDCE925PW 数据表(HTML) 12 Page - Texas Instruments |
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12 / 40 page ![]() 12 CDCE925, CDCEL925 SCAS847I – JULY 2007 – REVISED OCTOBER 2016 www.ti.com Product Folder Links: CDCE925 CDCEL925 Submit Documentation Feedback Copyright © 2007–2016, Texas Instruments Incorporated 9 Detailed Description 9.1 Overview The CDCE925 and CDCEL925 devices are modular PLL-based, low-cost, high-performance, programmable clock synthesizers, multipliers, and dividers. They generate up to five output clocks from a single input frequency. Each output can be programmed in-system for any clock frequency up to 230 MHz, using one of the two integrated configurable PLLs. The CDCx925 has separate output supply pins, VDDOUT, which is 1.8 V for CDCEL925 and 2.5 V to 3.3 V for CDCE925. The input accepts an external crystal or LVCMOS clock signal. If an external crystal is used, an on-chip load capacitor is adequate for most applications. The value of the load capacitor is programmable from 0 pF to 20 pF. Additionally, a selectable on-chip VCXO allows synchronization of the output frequency to an external control signal, that is, the PWM signal. The deep M/N divider ratio allows the generation of 0-ppm audio and video, networking (WLAN, Bluetooth, Ethernet, GPS), or interface (USB, IEEE1394, memory stick) clocks from a reference input frequency such as 27 MHz. All PLLs support spread-spectrum clocking (SSC). SSC can be center-spread or down-spread clocking. This is a common technique to reduce electro-magnetic interference (EMI). Based on the PLL frequency and the divider settings, the internal loop filter components are automatically adjusted to achieve high stability, and to optimize the jitter-transfer characteristic of each PLL. The device supports non-volatile EEPROM programming for easy customization of the device in the application. It is preset to a factory default configuration (see Default Device Setting). It can be reprogrammed to a different application configuration before PCB assembly, or reprogrammed by in-system programming. All device settings are programmable through the SDA and SCL bus, a 2-wire serial interface. Three free programmable control inputs, S0, S1, and S2, can be used to control various aspects of operation including frequency selection, changing the SSC parameters to lower EMI, PLL bypass, power down, or other control features like outputs disable to low, outputs in high-impedance state, and so forth. The CDCx925 operates in a 1.8-V environment. It operates within a temperature range of –40°C to 85°C. |
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