CDCE925PW datasheet(23/40 Pages) TI2

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CDCE925, CDCEL925

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SCAS847I – JULY 2007 – REVISED OCTOBER 2016

Product Folder Links: CDCE925 CDCEL925

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Table 11. PLL2 Configuration Register (continued)

OFFSET(1)

BIT(2)

ACRONYM

DEFAULT(3)

DESCRIPTION

(5)

PLL settings limits: 16

≤ q ≤ 63, 0 ≤ p ≤ 7, 0 ≤ r ≤ 511, 0 < N < 4096

25h

Y4Y5_7

Y4Y5_x output state selection(4)

Y4Y5_6

0 – state0 (predefined by Y4Y5_ST0)

1 – state1 (predefined by Y4Y5_ST1)

Y4Y5_5

Y4Y5_4

Y4Y5_3

Y4Y5_2

Y4Y5_1

Y4Y5_0

26h

SSC2DC

PLL2 SSC down/center selection:

0 – Down

1 – Center

6:0

Pdiv4

01h

7-Bit Y4-output-divider Pdiv4:

0 – Reset and in standby

1 to 127 – Divider value

27h

—

Reserved – do not write others than 0

6:0

Pdiv5

01h

7-bit Y5-output-divider Pdiv5:

0 – Reset and in standby

1 to 127 – Divider value

28h

7:0

PLL2_0N [11:4

004h

PLL2_0(5): 30-Bit Multiplier/Divider value for frequency fVCO2_0

(for more information, see PLL Multiplier/Divider Definition).

29h

7:4

PLL2_0N [3:0]

3:0

PLL2_0R [8:5]

000h

2Ah

7:3

PLL2_0R[4:0]

2:0

PLL2_0Q [5:3]

10h

2Bh

7:5

PLL2_0Q [2:0]

4:2

PLL2_0P [2:0]

010b

1:0

VCO2_0_RANGE

00b

fVCO2_0 range selection:

00 – fVCO2_0 < 125 MHz

01 – 125 MHz

≤ fVCO2_0 < 150 MHz

10 – 150 MHz

≤ fVCO2_0 < 175 MHz

11 – fVCO2_0 ≥ 175 MHz

2Ch

7:0

PLL2_1N [11:4]

004h

PLL2_1(5): 30-bit multiplier/divider value for frequency fVCO2_1

(for more information, see PLL Multiplier/Divider Definition).

2Dh

7:4

PLL2_1N [3:0]

3:0

PLL2_1R [8:5]

000h

2Eh

7:3

PLL2_1R[4:0]

2:0

PLL2_1Q [5:3]

10h

2Fh

7:5

PLL2_1Q [2:0]

4:2

PLL2_1P [2:0]

010b

1:0

VCO2_1_RANGE

00b

fVCO2_1 range selection:

00 – fVCO2_1 < 125 MHz

01 – 125 MHz

≤ fVCO2_1 < 150 MHz

10 – 150 MHz

≤ fVCO2_1 < 175 MHz

11 – fVCO2_1 ≥ 175 MHz

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