1

7

1

1

1

1

1

1

S

Slave Address

Wr

A

A

Sr

Rd

A

8

1

1

1

1

ByteCountN

A

A

A

P

DataByte0

…

DataByteN-1

8

CommandCode

7

Slave Address

8

8

1

7

1

1

1

1

S

Slave Address

Wr

A

A

A

8

1

1

1

1

DataByte0

A

A

A

P

8

DataByteN-1

…

8

DataByte1

8

CommandCode

ByteCount=N

8

1

7

1

1

1

1

1

1

S

Slave Address

Wr

A

A

Sr

Rd

A

8

1

1

Data Byte

A

P

CommandCode

8

7

Slave Address

18

CDCE925, CDCEL925

SCAS847I – JULY 2007 – REVISED OCTOBER 2016

www.ti.com

Product Folder Links: CDCE925 CDCEL925

Submit Documentation Feedback

Copyright © 2007–2016, Texas Instruments Incorporated

Figure 12. Byte Read Protocol

Data byte 0 bits [7:0] is reserved for Revision Code and Vendor Identification. Also, it is used for internal test purpose

and must not be overwritten.

Figure 13. Block Write Protocol

Figure 14. Block Read Protocol

9.6 Register Maps

9.6.1 SDA/SCL Configuration Registers

The clock input, control pins, PLLs, and output stages are user configurable. The following tables and

explanations describe the programmable functions of the CDCEx925. All settings can be manually written into

the device through the SDA/SCL bus or easily programmed by using the TI Pro-Clock™ software. TI Pro-Clock

software allows the user to quickly make all settings and automatically calculates the values for optimized

performance at lowest jitter.

Table 7. SDA/SCL Registers

ADDRESS OFFSET

REGISTER DESCRIPTION

TABLE

00h

Generic configuration register

Table 9

10h

PLL1 configuration register

Table 10

20h

PLL2 configuration register

Table 11