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CDCE925PW 数据表(PDF) 17 Page - Texas Instruments |
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CDCE925PW 数据表(HTML) 17 Page - Texas Instruments |
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17 / 40 page ![]() 1 7 1 1 8 1 1 1 S Slave Address Wr A A A P DataByte CommandCode 8 1 7 1 1 8 1 1 S Slave Address A DataByte A P MSB LSB MSB LSB S StartCondition Sr RepeatedStartCondition 1=Read(Rd)FromCDCE9xxDevice;0=Write(Wr)toCDCE9xxx A Acknowledge(ACK=0andNACK=1) P StopCondition Master-to-Slave Transmission Slave-to-Master Transmission R/W R/W CDCE925 CDCEL925 Slave Master SDA SCL R P R P C BUS C BUS Copyright © 2016, Texas Instruments Incorporated 17 CDCE925, CDCEL925 www.ti.com SCAS847I – JULY 2007 – REVISED OCTOBER 2016 Product Folder Links: CDCE925 CDCEL925 Submit Documentation Feedback Copyright © 2007–2016, Texas Instruments Incorporated Device Functional Modes (continued) Figure 9. SDA/SCL Hardware Interface 9.5 Programming Table 6. Command Code Definition BIT DESCRIPTION 7 0 = Block Read or Block Write operation 1 = Byte Read or Byte Write operation (6:0) Byte offset for Byte Read, Block Read, Byte Write and Block Write operations. Figure 10. Generic Programming Sequence Figure 11. Byte Write Protocol |
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