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CDCE925, CDCEL925

SCAS847I – JULY 2007 – REVISED OCTOBER 2016

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Product Folder Links: CDCE925 CDCEL925

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Copyright © 2007–2016, Texas Instruments Incorporated

Typical Application (continued)

Figure 22. Output Spectrum With SSC Off

Figure 23. Output Spectrum With SSC On, 2% Center

11 Power Supply Recommendations

There is no restriction on the power-up sequence. In case the VDDOUT is applied first, TI recommends grounding

VDD. In case the VDDOUT is powered while VDD is floating, there is a risk of high current flowing on the VDDOUT.

The device has a power-up control that is connected to the 1.8-V supply. This keeps the whole device disabled

until the 1.8-V supply reaches a sufficient voltage level. Then the device switches on all internal components,

including the outputs. If there is a 3.3-V VDDOUT available before the 1.8-V, the outputs stay disabled until the 1.8-

V supply reaches a certain level.

12 Layout

12.1 Layout Guidelines

When the CDCEx937 is used as a crystal buffer, any parasitics across the crystal affects the pulling range of the

VCXO. Therefore, take care in placing the crystal units on the board. Crystals must be placed as close to the

device as possible, ensuring that the routing lines from the crystal terminals to XIN and XOUT have the same

length.

If possible, cut out both ground plane and power plane under the area where the crystal and the routing to the

device are placed. In this area, always avoid routing any other signal line, as it could be a source of noise

coupling.

Additional discrete capacitors can be required to meet the load capacitance specification of certain crystal. For

example, a 10.7-pF load capacitor is not fully programmable on the chip, because the internal capacitor can

range from 0 pF to 20 pF with steps of 1 pF. The 0.7-pF capacitor therefore can be discretely added on top of an

internal 10-pF capacitor.

To minimize the inductive influence of the trace, TI recommends placing this small capacitor as close to the

device as possible and symmetrically with respect to XIN and XOUT.

Figure 24 shows a conceptual layout detailing recommended placement of power supply bypass capacitors on

the basis of CDCEx937. For component side mounting, use 0402 body size capacitors to facilitate signal routing.

Keep the connections between the bypass capacitors and the power supply on the device as short as possible.

Ground the other side of the capacitor using a low-impedance connection to the ground plane.