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STA382BWSTR 数据表(PDF) 46 Page - STMicroelectronics |
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STA382BWSTR 数据表(HTML) 46 Page - STMicroelectronics |
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46 / 172 page  Register description: New Map STA382BWS 46/172 Doc ID 022784 Rev 1 6.1 CLK register (addr 0x00) Table 15. CLK register 6.2 STATUS register (addr 0x01) D7 D6 D5 D4 D3 D2 D1 D0 CLK_CFG[3:0] Reserved Reserved Reserved I2S 00 00 00 0 0 Bit R/W RST Name Description 7R/W 0 CLK_CFG[3:0] 0000: 44.1/48 kHz BITCLK = 64 Fs 0001: 32 kHz BITCLK = 64 Fs 0010: 96 kHz BITCLK = 64 Fs 0011: 48/44.1/32 kHz MCK = 256 Fs others: clock configuration depends on IR/MCS bits 6R/W 0 5R/W 0 4R/W 0 0R/W 0 I2S ‘0’ = SAI configured in I2S mode ‘1’ = SAI configuration depends on CONFB register status D7 D6 D5 D4 D3 D2 D1 D0 FAULT DRCCRC EQCRC BADPWM Reserved Reserved I2SERR PLLUL NA NA NA NA NA NA NA NA Table 16. STATUS register Bit R/W RST Name Description 7R FAULT(1) 1. Fault status is set to 1 once the power bridge goes to tri-state mode. ‘0’ = the power bridge is in fault condition ‘1’ = the power bridge is in normal condition 6 R DRCCRC ‘0’ = normal operation ‘1’ = CRC error on DRC BIQUADS 5 R EQCRC ‘0’ = normal operation ‘1’ = CRC error on BIQUADS 4R BADPWM ‘0’ = normal operation ‘1’ = PWM outputs are invalid 1 R I2SERR ‘0’ = normal operation ‘1’ = SAI interface error detected (see Section 6.14: Configuration register B (addr 0x12)) 0 R PLLUL ‘0’ = PLL is locked ‘1’ = PLL is not locked Obsolete Product(s) - Obsolete Product(s) |
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