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STA382BWSTR 数据表(PDF) 72 Page - STMicroelectronics |
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STA382BWSTR 数据表(HTML) 72 Page - STMicroelectronics |
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72 / 172 page ![]() Register description: New Map STA382BWS 72/172 Doc ID 022784 Rev 1 6.21.2 EQ bypass EQ control can be bypassed on a per-channel basis for channels 1 and 2. If EQ control is bypassed on a given channel, the prescale and all filters (biquads, bass, treble in any combination) are bypassed for that channel. 6.21.3 Volume bypass Each channel contains an individual channel volume bypass. If a particular channel has volume bypassed via the CxVBP = 1 register, then only the channel volume setting for that particular channel affects the volume setting, the master volume setting will not affect that channel. Table 63. Volume bypass register 6.21.4 Binary output enable registers Each individual channel output can be set to output a binary PWM stream. In this mode output A of a channel is considered the positive output and output B is the negative inverse. 6.21.5 Limiter select Limiter selection can be made on a per-channel basis according to the channel limiter select bits. CxLS bits are not considered in case of dual-band DRC (Section 6.11.1: Dual-band DRC), EQ DRC (Section 6.26.1: Extended post-scale range) usage. Table 62. EQ bypass CxEQBP Mode 0 Perform EQ on channel x - normal operation 1 Bypass EQ on channel x CxVBP Mode 0 Normal volume operations 1 Volume is bypassed Table 64. Binary output enable registers CxBO Mode 0 FFX 3-state output - normal operation 1 Binary output Table 65. Channel limiter mapping as a function of C3LS bits C3LS[1:0] Channel limiter mapping 00 Channel has limiting disabled 01 Channel is mapped to limiter #1 10 Channel is mapped to limiter #2 Obsolete Product(s) - Obsolete Product(s) |
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