STA382BWSTR datasheet(9/172 Pages) STMICROELECTRONICS

9 / 172 page

STA382BWS

Contents

Doc ID 022784 Rev 1

9/172

7.16.1

Dual-band DRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

7.16.2

Extended post-scale range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

7.16.3

Extended attack rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

7.16.4

Extended BIQUAD selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

7.17

EQ soft volume configuration registers (addr 0x37 - 0x38) . . . . . . . . . . 146

7.18

Extra volume resolution configuration registers (address 0x3F; 0x40) . . 147

7.19

PLL configuration registers

(address 0x41; 0x42; 0x43; 0x44; 0x45; 0X46) . . . . . . . . . . . . . . . . . . . 148

7.20

Short-circuit protection mode registers SHOK (address 0x47) . . . . . . . 150

7.21

Extended coefficient range up to -4...4 (address 0x49, 0x4A) . . . . . . . . 152

7.22

Miscellaneous registers (address 0x4B, 0x4C) . . . . . . . . . . . . . . . . . . . 152

7.22.1

Rate power-down enable (RPDNEN) bit (address 0x4B, bit D7) . . . . . 152

7.22.2

Bridge immediately off (BRIDGOFF) bit (address 0x4B, bit D5) . . . . . 153

7.22.3

Channel PWM enable (CPWMEN) bit (address 0x4B, bit D2) . . . . . . . 153

7.22.4

External amplifier hardware pin enabler (LPDP, LPD LPDE) bits

(address 0x4C, bit D7, D6, D5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

7.22.5

Power-down delay selector (PNDLSL[2:0]) bits

(address 0x4C, bit D4, D3, D2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

7.22.6

Short-circuit check enable bit (address 0x4C, bit D0) . . . . . . . . . . . . . 154

7.23

Bad PWM detection registers (address 0x4D, 0x4E, 0x4F) . . . . . . . . . . 155

7.24

Enhanced zero-detect mute and input level measurement

(address 0x50-0x54, 0x2E, 0x2F and 0x5E) . . . . . . . . . . . . . . . . . . . . . 156

7.25

Headphone/Line out configuration register (address 0x55) . . . . . . . . . . 158

7.26

F3XCFG (address 0x58; 0x59) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

7.27

STCompressorTM configuration register (address 0x5A; 0x5B) . . . . . . . 160

7.28

Charge pump synchronization (address 0x5F) . . . . . . . . . . . . . . . . . . . 161

7.29

Coefficient RAM CRC protection (address 0x60-0x6C) . . . . . . . . . . . . . 162

7.30

MISC3 (address 0x6E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

7.31

MISC4 (address 0x7E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

8.1

Application schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

8.2

Headphone and 2 Vrms line out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

8.3

Typical output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Obsolete

Product(s)

- Obsolete

Product(s)

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