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STA382BWSTR 数据表(PDF) 68 Page - STMicroelectronics |
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STA382BWSTR 数据表(HTML) 68 Page - STMicroelectronics |
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68 / 172 page ![]() Register description: New Map STA382BWS 68/172 Doc ID 022784 Rev 1 6.19 Volume control registers (addr 0x17 - 0x1B) 6.19.1 Mute/line output configuration register (addr 0x17) Line output is only active when OCFG = 00. In this case LOC determines the line output configuration. The source of the line output is always the channel 1 and 2 inputs. Table 55. Mute configuration D7 D6 D5 D4 D3 D2 D1 D0 LOC1 LOC0 Reserved Reserved C3M C2M C1M MMUTE 00 00 00 0 0 Table 54. Line output configuration LOC[1:0] Line output configuration 00 Line output fixed - no volume, no EQ 01 Line output variable - CH3 volume effects line output, no EQ 10 Line output variable with EQ - CH3 volume effects line output 11 Reserved Bit R/W RST Name Description 3R/W 0 C3M Channel 3 mute 0 - No mute condition. It is possible to set the channel volume 1 - Channel 3 in hardware mute 2R/W 0 C2M Channel 2 mute 0 - No mute condition. It is possible to set the channel volume 1 - Channel 2 in hardware mute 1R/W 0 C1M Channel 1 mute 0 - No mute condition. It is possible to set the channel volume 1 - Channel 1 in hardware mute 0 R/W 0 MMUTE Master mute 0 - Normal operation 1 - All channels are in mute condition Obsolete Product(s) - Obsolete Product(s) |
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